clk-lgm.c (036177310bac5534de44ff6a7b60a4d2c0b6567c) clk-lgm.c (eaabee88a88a26b108be8d120fc072dfaf462cef)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
4 * Copyright (C) 2020 Intel Corporation.
5 * Zhu Yixin <yzhu@maxlinear.com>
6 * Rahul Tanwar <rtanwar@maxlinear.com>
7 */
8#include <linux/clk-provider.h>

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439 if (IS_ERR_OR_NULL(ctx->membase)) {
440 dev_err(dev, "Failed to get clk CGU iomem\n");
441 return PTR_ERR(ctx->membase);
442 }
443
444
445 ctx->np = np;
446 ctx->dev = dev;
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
4 * Copyright (C) 2020 Intel Corporation.
5 * Zhu Yixin <yzhu@maxlinear.com>
6 * Rahul Tanwar <rtanwar@maxlinear.com>
7 */
8#include <linux/clk-provider.h>

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439 if (IS_ERR_OR_NULL(ctx->membase)) {
440 dev_err(dev, "Failed to get clk CGU iomem\n");
441 return PTR_ERR(ctx->membase);
442 }
443
444
445 ctx->np = np;
446 ctx->dev = dev;
447 spin_lock_init(&ctx->lock);
448
449 ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
450 ARRAY_SIZE(lgm_pll_clks));
451 if (ret)
452 return ret;
453
454 ret = lgm_clk_register_branches(ctx, lgm_branch_clks,
455 ARRAY_SIZE(lgm_branch_clks));

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448 ret = lgm_clk_register_plls(ctx, lgm_pll_clks,
449 ARRAY_SIZE(lgm_pll_clks));
450 if (ret)
451 return ret;
452
453 ret = lgm_clk_register_branches(ctx, lgm_branch_clks,
454 ARRAY_SIZE(lgm_branch_clks));

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