clk-cgu.h (036177310bac5534de44ff6a7b60a4d2c0b6567c) clk-cgu.h (eaabee88a88a26b108be8d120fc072dfaf462cef)
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
4 * Copyright (C) 2020 Intel Corporation.
5 * Zhu Yixin <yzhu@maxlinear.com>
6 * Rahul Tanwar <rtanwar@maxlinear.com>
7 */
8

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13
14struct lgm_clk_mux {
15 struct clk_hw hw;
16 struct regmap *membase;
17 unsigned int reg;
18 u8 shift;
19 u8 width;
20 unsigned long flags;
1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (C) 2020-2022 MaxLinear, Inc.
4 * Copyright (C) 2020 Intel Corporation.
5 * Zhu Yixin <yzhu@maxlinear.com>
6 * Rahul Tanwar <rtanwar@maxlinear.com>
7 */
8

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13
14struct lgm_clk_mux {
15 struct clk_hw hw;
16 struct regmap *membase;
17 unsigned int reg;
18 u8 shift;
19 u8 width;
20 unsigned long flags;
21 spinlock_t lock;
22};
23
24struct lgm_clk_divider {
25 struct clk_hw hw;
26 struct regmap *membase;
27 unsigned int reg;
28 u8 shift;
29 u8 width;
30 u8 shift_gate;
31 u8 width_gate;
32 unsigned long flags;
33 const struct clk_div_table *table;
21};
22
23struct lgm_clk_divider {
24 struct clk_hw hw;
25 struct regmap *membase;
26 unsigned int reg;
27 u8 shift;
28 u8 width;
29 u8 shift_gate;
30 u8 width_gate;
31 unsigned long flags;
32 const struct clk_div_table *table;
34 spinlock_t lock;
35};
36
37struct lgm_clk_ddiv {
38 struct clk_hw hw;
39 struct regmap *membase;
40 unsigned int reg;
41 u8 shift0;
42 u8 width0;
43 u8 shift1;
44 u8 width1;
45 u8 shift2;
46 u8 width2;
47 u8 shift_gate;
48 u8 width_gate;
49 unsigned int mult;
50 unsigned int div;
51 unsigned long flags;
33};
34
35struct lgm_clk_ddiv {
36 struct clk_hw hw;
37 struct regmap *membase;
38 unsigned int reg;
39 u8 shift0;
40 u8 width0;
41 u8 shift1;
42 u8 width1;
43 u8 shift2;
44 u8 width2;
45 u8 shift_gate;
46 u8 width_gate;
47 unsigned int mult;
48 unsigned int div;
49 unsigned long flags;
52 spinlock_t lock;
53};
54
55struct lgm_clk_gate {
56 struct clk_hw hw;
57 struct regmap *membase;
58 unsigned int reg;
59 u8 shift;
60 unsigned long flags;
50};
51
52struct lgm_clk_gate {
53 struct clk_hw hw;
54 struct regmap *membase;
55 unsigned int reg;
56 u8 shift;
57 unsigned long flags;
61 spinlock_t lock;
62};
63
64enum lgm_clk_type {
65 CLK_TYPE_FIXED,
66 CLK_TYPE_MUX,
67 CLK_TYPE_DIVIDER,
68 CLK_TYPE_FIXED_FACTOR,
69 CLK_TYPE_GATE,

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77 * @dev: device
78 * @clk_data: array of hw clocks and clk number.
79 */
80struct lgm_clk_provider {
81 struct regmap *membase;
82 struct device_node *np;
83 struct device *dev;
84 struct clk_hw_onecell_data clk_data;
58};
59
60enum lgm_clk_type {
61 CLK_TYPE_FIXED,
62 CLK_TYPE_MUX,
63 CLK_TYPE_DIVIDER,
64 CLK_TYPE_FIXED_FACTOR,
65 CLK_TYPE_GATE,

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73 * @dev: device
74 * @clk_data: array of hw clocks and clk number.
75 */
76struct lgm_clk_provider {
77 struct regmap *membase;
78 struct device_node *np;
79 struct device *dev;
80 struct clk_hw_onecell_data clk_data;
85 spinlock_t lock;
86};
87
88enum pll_type {
89 TYPE_ROPLL,
90 TYPE_LJPLL,
91 TYPE_NONE,
92};
93
94struct lgm_clk_pll {
95 struct clk_hw hw;
96 struct regmap *membase;
97 unsigned int reg;
98 unsigned long flags;
99 enum pll_type type;
81};
82
83enum pll_type {
84 TYPE_ROPLL,
85 TYPE_LJPLL,
86 TYPE_NONE,
87};
88
89struct lgm_clk_pll {
90 struct clk_hw hw;
91 struct regmap *membase;
92 unsigned int reg;
93 unsigned long flags;
94 enum pll_type type;
100 spinlock_t lock;
101};
102
103/**
104 * struct lgm_pll_clk_data
105 * @id: platform specific id of the clock.
106 * @name: name of this pll clock.
107 * @parent_data: parent clock data.
108 * @num_parents: number of parents.

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96
97/**
98 * struct lgm_pll_clk_data
99 * @id: platform specific id of the clock.
100 * @name: name of this pll clock.
101 * @parent_data: parent clock data.
102 * @num_parents: number of parents.

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