clk-tegra30.c (415d2b3392d7a80903e0f97f051201aa02bf20e9) clk-tegra30.c (845d782d91448e0fbca686bca2cc9f9c2a9ba3e7)
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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1262 { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
1263 { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
1264 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
1265 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1266 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1267 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
1268 { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
1269 { TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
1/*
2 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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1262 { TEGRA30_CLK_DISP1, TEGRA30_CLK_PLL_P, 600000000, 0 },
1263 { TEGRA30_CLK_DISP2, TEGRA30_CLK_PLL_P, 600000000, 0 },
1264 { TEGRA30_CLK_TWD, TEGRA30_CLK_CLK_MAX, 0, 1 },
1265 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1266 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1267 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
1268 { TEGRA30_CLK_PLL_U, TEGRA30_CLK_CLK_MAX, 480000000, 0 },
1269 { TEGRA30_CLK_VDE, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
1270 { TEGRA30_CLK_SPDIF_IN_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1271 { TEGRA30_CLK_I2S0_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1272 { TEGRA30_CLK_I2S1_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1273 { TEGRA30_CLK_I2S2_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1274 { TEGRA30_CLK_I2S3_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1275 { TEGRA30_CLK_I2S4_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1276 { TEGRA30_CLK_VIMCLK_SYNC, TEGRA30_CLK_CLK_MAX, 24000000, 0 },
1270 /* must be the last entry */
1271 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
1272};
1273
1274static void __init tegra30_clock_apply_init_table(void)
1275{
1276 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1277}

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1339 return;
1340
1341 tegra_fixed_clk_init(tegra30_clks);
1342 tegra30_pll_init();
1343 tegra30_super_clk_init();
1344 tegra30_periph_clk_init();
1345 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
1346 tegra30_audio_plls,
1277 /* must be the last entry */
1278 { TEGRA30_CLK_CLK_MAX, TEGRA30_CLK_CLK_MAX, 0, 0 },
1279};
1280
1281static void __init tegra30_clock_apply_init_table(void)
1282{
1283 tegra_init_from_table(init_table, clks, TEGRA30_CLK_CLK_MAX);
1284}

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1346 return;
1347
1348 tegra_fixed_clk_init(tegra30_clks);
1349 tegra30_pll_init();
1350 tegra30_super_clk_init();
1351 tegra30_periph_clk_init();
1352 tegra_audio_clk_init(clk_base, pmc_base, tegra30_clks,
1353 tegra30_audio_plls,
1347 ARRAY_SIZE(tegra30_audio_plls));
1354 ARRAY_SIZE(tegra30_audio_plls), 24000000);
1348 tegra_pmc_clk_init(pmc_base, tegra30_clks);
1349
1350 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1351
1352 tegra_add_of_provider(np, of_clk_src_onecell_get);
1353 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1354
1355 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1356
1357 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1358}
1359CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);
1355 tegra_pmc_clk_init(pmc_base, tegra30_clks);
1356
1357 tegra_init_dup_clks(tegra_clk_duplicates, clks, TEGRA30_CLK_CLK_MAX);
1358
1359 tegra_add_of_provider(np, of_clk_src_onecell_get);
1360 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1361
1362 tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
1363
1364 tegra_cpu_car_ops = &tegra30_cpu_car_ops;
1365}
1366CLK_OF_DECLARE(tegra30, "nvidia,tegra30-car", tegra30_clock_init);