clk-tegra210.c (cd4d6f357545bc03112265b19e5ed50592812986) | clk-tegra210.c (a3cba697a2a09e6769996d5265991a3228004d92) |
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1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#include <linux/io.h> 7#include <linux/clk.h> 8#include <linux/clk-provider.h> --- 23 unchanged lines hidden (view full) --- 32 33#define CLK_SOURCE_CSITE 0x1d4 34#define CLK_SOURCE_EMC 0x19c 35#define CLK_SOURCE_SOR1 0x410 36#define CLK_SOURCE_SOR0 0x414 37#define CLK_SOURCE_LA 0x1f8 38#define CLK_SOURCE_SDMMC2 0x154 39#define CLK_SOURCE_SDMMC4 0x164 | 1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 4 */ 5 6#include <linux/io.h> 7#include <linux/clk.h> 8#include <linux/clk-provider.h> --- 23 unchanged lines hidden (view full) --- 32 33#define CLK_SOURCE_CSITE 0x1d4 34#define CLK_SOURCE_EMC 0x19c 35#define CLK_SOURCE_SOR1 0x410 36#define CLK_SOURCE_SOR0 0x414 37#define CLK_SOURCE_LA 0x1f8 38#define CLK_SOURCE_SDMMC2 0x154 39#define CLK_SOURCE_SDMMC4 0x164 |
40#define CLK_SOURCE_EMC_DLL 0x664 |
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40 41#define PLLC_BASE 0x80 42#define PLLC_OUT 0x84 43#define PLLC_MISC0 0x88 44#define PLLC_MISC1 0x8c 45#define PLLC_MISC2 0x5d0 46#define PLLC_MISC3 0x5d4 47 --- 174 unchanged lines hidden (view full) --- 222#define CLK_M_DIVISOR_MASK 0x3 223 224#define CLK_MASK_ARM 0x44 225#define MISC_CLK_ENB 0x48 226 227#define RST_DFLL_DVCO 0x2f4 228#define DVFS_DFLL_RESET_SHIFT 0 229 | 41 42#define PLLC_BASE 0x80 43#define PLLC_OUT 0x84 44#define PLLC_MISC0 0x88 45#define PLLC_MISC1 0x8c 46#define PLLC_MISC2 0x5d0 47#define PLLC_MISC3 0x5d4 48 --- 174 unchanged lines hidden (view full) --- 223#define CLK_M_DIVISOR_MASK 0x3 224 225#define CLK_MASK_ARM 0x44 226#define MISC_CLK_ENB 0x48 227 228#define RST_DFLL_DVCO 0x2f4 229#define DVFS_DFLL_RESET_SHIFT 0 230 |
231#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET 0x284 232#define CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR 0x288 233#define CLK_OUT_ENB_X_CLK_ENB_EMC_DLL BIT(14) 234 |
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230#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 231#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac 232#define CPU_SOFTRST_CTRL 0x380 233 234#define LVL2_CLK_GATE_OVRA 0xf8 235#define LVL2_CLK_GATE_OVRC 0x3a0 236#define LVL2_CLK_GATE_OVRD 0x3a4 237#define LVL2_CLK_GATE_OVRE 0x554 --- 312 unchanged lines hidden (view full) --- 550 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; 551 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; 552 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; 553 } 554 writel_relaxed(val, clk_base + SATA_PLL_CFG0); 555} 556EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw); 557 | 235#define CLK_RST_CONTROLLER_RST_DEV_Y_SET 0x2a8 236#define CLK_RST_CONTROLLER_RST_DEV_Y_CLR 0x2ac 237#define CPU_SOFTRST_CTRL 0x380 238 239#define LVL2_CLK_GATE_OVRA 0xf8 240#define LVL2_CLK_GATE_OVRC 0x3a0 241#define LVL2_CLK_GATE_OVRD 0x3a4 242#define LVL2_CLK_GATE_OVRE 0x554 --- 312 unchanged lines hidden (view full) --- 555 val &= ~SATA_PLL_CFG0_SATA_SEQ_RESET_INPUT_VALUE; 556 val &= ~SATA_PLL_CFG0_SATA_SEQ_LANE_PD_INPUT_VALUE; 557 val &= ~SATA_PLL_CFG0_SATA_SEQ_PADPLL_PD_INPUT_VALUE; 558 } 559 writel_relaxed(val, clk_base + SATA_PLL_CFG0); 560} 561EXPORT_SYMBOL_GPL(tegra210_set_sata_pll_seq_sw); 562 |
563void tegra210_clk_emc_dll_enable(bool flag) 564{ 565 u32 offset = flag ? CLK_RST_CONTROLLER_CLK_OUT_ENB_X_SET : 566 CLK_RST_CONTROLLER_CLK_OUT_ENB_X_CLR; 567 568 writel_relaxed(CLK_OUT_ENB_X_CLK_ENB_EMC_DLL, clk_base + offset); 569} 570EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_enable); 571 572void tegra210_clk_emc_dll_update_setting(u32 emc_dll_src_value) 573{ 574 writel_relaxed(emc_dll_src_value, clk_base + CLK_SOURCE_EMC_DLL); 575} 576EXPORT_SYMBOL_GPL(tegra210_clk_emc_dll_update_setting); 577 578void tegra210_clk_emc_update_setting(u32 emc_src_value) 579{ 580 writel_relaxed(emc_src_value, clk_base + CLK_SOURCE_EMC); 581} 582EXPORT_SYMBOL_GPL(tegra210_clk_emc_update_setting); 583 |
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558static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist) 559{ 560 u32 val; 561 562 val = readl_relaxed(clk_base + mbist->lvl2_offset); 563 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); 564 fence_udelay(1, clk_base); 565 writel_relaxed(val, clk_base + mbist->lvl2_offset); --- 3155 unchanged lines hidden --- | 584static void tegra210_generic_mbist_war(struct tegra210_domain_mbist_war *mbist) 585{ 586 u32 val; 587 588 val = readl_relaxed(clk_base + mbist->lvl2_offset); 589 writel_relaxed(val | mbist->lvl2_mask, clk_base + mbist->lvl2_offset); 590 fence_udelay(1, clk_base); 591 writel_relaxed(val, clk_base + mbist->lvl2_offset); --- 3155 unchanged lines hidden --- |