clk-tegra210.c (9d066a252786e1a18484a6283f82614d42a9f4ac) clk-tegra210.c (2e34c2ac16ee6574743c73caa3d796e307f028a6)
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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1361 return 1 << i;
1362 }
1363 }
1364 return -EINVAL;
1365}
1366
1367static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1368 /* 1 GHz */
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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1361 return 1 << i;
1362 }
1363 }
1364 return -EINVAL;
1365}
1366
1367static struct tegra_clk_pll_freq_table pll_x_freq_table[] = {
1368 /* 1 GHz */
1369 { 12000000, 1000000000, 166, 1, 1, 0 }, /* actual: 996.0 MHz */
1370 { 13000000, 1000000000, 153, 1, 1, 0 }, /* actual: 994.0 MHz */
1371 { 38400000, 1000000000, 156, 3, 1, 0 }, /* actual: 998.4 MHz */
1369 { 12000000, 1000000000, 166, 1, 2, 0 }, /* actual: 996.0 MHz */
1370 { 13000000, 1000000000, 153, 1, 2, 0 }, /* actual: 994.0 MHz */
1371 { 38400000, 1000000000, 156, 3, 2, 0 }, /* actual: 998.4 MHz */
1372 { 0, 0, 0, 0, 0, 0 },
1373};
1374
1375static struct tegra_clk_pll_params pll_x_params = {
1376 .input_min = 12000000,
1377 .input_max = 800000000,
1378 .cf_min = 12000000,
1379 .cf_max = 38400000,

--- 32 unchanged lines hidden (view full) ---

1412 .divm_width = 8,
1413 .divn_shift = 10,
1414 .divn_width = 8,
1415 .divp_shift = 20,
1416 .divp_width = 5,
1417};
1418
1419static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1372 { 0, 0, 0, 0, 0, 0 },
1373};
1374
1375static struct tegra_clk_pll_params pll_x_params = {
1376 .input_min = 12000000,
1377 .input_max = 800000000,
1378 .cf_min = 12000000,
1379 .cf_max = 38400000,

--- 32 unchanged lines hidden (view full) ---

1412 .divm_width = 8,
1413 .divn_shift = 10,
1414 .divn_width = 8,
1415 .divp_shift = 20,
1416 .divp_width = 5,
1417};
1418
1419static struct tegra_clk_pll_freq_table pll_cx_freq_table[] = {
1420 { 12000000, 510000000, 85, 1, 1, 0 },
1421 { 13000000, 510000000, 78, 1, 1, 0 }, /* actual: 507.0 MHz */
1422 { 38400000, 510000000, 79, 3, 1, 0 }, /* actual: 505.6 MHz */
1420 { 12000000, 510000000, 85, 1, 2, 0 },
1421 { 13000000, 510000000, 78, 1, 2, 0 }, /* actual: 507.0 MHz */
1422 { 38400000, 510000000, 79, 3, 2, 0 }, /* actual: 505.6 MHz */
1423 { 0, 0, 0, 0, 0, 0 },
1424};
1425
1426static struct tegra_clk_pll_params pll_c_params = {
1427 .input_min = 12000000,
1428 .input_max = 700000000,
1429 .cf_min = 12000000,
1430 .cf_max = 50000000,

--- 96 unchanged lines hidden (view full) ---

1527 .divm_width = 8,
1528 .divn_shift = 8,
1529 .divn_width = 8,
1530 .divp_shift = 19,
1531 .divp_width = 5,
1532};
1533
1534static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1423 { 0, 0, 0, 0, 0, 0 },
1424};
1425
1426static struct tegra_clk_pll_params pll_c_params = {
1427 .input_min = 12000000,
1428 .input_max = 700000000,
1429 .cf_min = 12000000,
1430 .cf_max = 50000000,

--- 96 unchanged lines hidden (view full) ---

1527 .divm_width = 8,
1528 .divn_shift = 8,
1529 .divn_width = 8,
1530 .divp_shift = 19,
1531 .divp_width = 5,
1532};
1533
1534static struct tegra_clk_pll_freq_table pll_c4_vco_freq_table[] = {
1535 { 12000000, 600000000, 50, 1, 0, 0 },
1536 { 13000000, 600000000, 46, 1, 0, 0 }, /* actual: 598.0 MHz */
1537 { 38400000, 600000000, 62, 4, 0, 0 }, /* actual: 595.2 MHz */
1535 { 12000000, 600000000, 50, 1, 1, 0 },
1536 { 13000000, 600000000, 46, 1, 1, 0 }, /* actual: 598.0 MHz */
1537 { 38400000, 600000000, 62, 4, 1, 0 }, /* actual: 595.2 MHz */
1538 { 0, 0, 0, 0, 0, 0 },
1539};
1540
1541static const struct clk_div_table pll_vco_post_div_table[] = {
1542 { .val = 0, .div = 1 },
1543 { .val = 1, .div = 2 },
1544 { .val = 2, .div = 3 },
1545 { .val = 3, .div = 4 },

--- 32 unchanged lines hidden (view full) ---

1578 .div_nmp = &pllss_nmp,
1579 .freq_table = pll_c4_vco_freq_table,
1580 .set_defaults = tegra210_pllc4_set_defaults,
1581 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1582 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1583};
1584
1585static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1538 { 0, 0, 0, 0, 0, 0 },
1539};
1540
1541static const struct clk_div_table pll_vco_post_div_table[] = {
1542 { .val = 0, .div = 1 },
1543 { .val = 1, .div = 2 },
1544 { .val = 2, .div = 3 },
1545 { .val = 3, .div = 4 },

--- 32 unchanged lines hidden (view full) ---

1578 .div_nmp = &pllss_nmp,
1579 .freq_table = pll_c4_vco_freq_table,
1580 .set_defaults = tegra210_pllc4_set_defaults,
1581 .flags = TEGRA_PLL_USE_LOCK | TEGRA_PLL_VCO_OUT,
1582 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1583};
1584
1585static struct tegra_clk_pll_freq_table pll_m_freq_table[] = {
1586 { 12000000, 800000000, 66, 1, 0, 0 }, /* actual: 792.0 MHz */
1587 { 13000000, 800000000, 61, 1, 0, 0 }, /* actual: 793.0 MHz */
1588 { 38400000, 297600000, 93, 4, 2, 0 },
1589 { 38400000, 400000000, 125, 4, 2, 0 },
1590 { 38400000, 532800000, 111, 4, 1, 0 },
1591 { 38400000, 665600000, 104, 3, 1, 0 },
1592 { 38400000, 800000000, 125, 3, 1, 0 },
1593 { 38400000, 931200000, 97, 4, 0, 0 },
1594 { 38400000, 1065600000, 111, 4, 0, 0 },
1595 { 38400000, 1200000000, 125, 4, 0, 0 },
1596 { 38400000, 1331200000, 104, 3, 0, 0 },
1597 { 38400000, 1459200000, 76, 2, 0, 0 },
1598 { 38400000, 1600000000, 125, 3, 0, 0 },
1586 { 12000000, 800000000, 66, 1, 1, 0 }, /* actual: 792.0 MHz */
1587 { 13000000, 800000000, 61, 1, 1, 0 }, /* actual: 793.0 MHz */
1588 { 38400000, 297600000, 93, 4, 3, 0 },
1589 { 38400000, 400000000, 125, 4, 3, 0 },
1590 { 38400000, 532800000, 111, 4, 2, 0 },
1591 { 38400000, 665600000, 104, 3, 2, 0 },
1592 { 38400000, 800000000, 125, 3, 2, 0 },
1593 { 38400000, 931200000, 97, 4, 1, 0 },
1594 { 38400000, 1065600000, 111, 4, 1, 0 },
1595 { 38400000, 1200000000, 125, 4, 1, 0 },
1596 { 38400000, 1331200000, 104, 3, 1, 0 },
1597 { 38400000, 1459200000, 76, 2, 1, 0 },
1598 { 38400000, 1600000000, 125, 3, 1, 0 },
1599 { 0, 0, 0, 0, 0, 0 },
1600};
1601
1602static struct div_nmp pllm_nmp = {
1603 .divm_shift = 0,
1604 .divm_width = 8,
1605 .override_divm_shift = 0,
1606 .divn_shift = 8,

--- 93 unchanged lines hidden (view full) ---

1700 .freq_table = pll_e_freq_table,
1701 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1702 TEGRA_PLL_HAS_LOCK_ENABLE,
1703 .fixed_rate = 100000000,
1704 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1705};
1706
1707static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1599 { 0, 0, 0, 0, 0, 0 },
1600};
1601
1602static struct div_nmp pllm_nmp = {
1603 .divm_shift = 0,
1604 .divm_width = 8,
1605 .override_divm_shift = 0,
1606 .divn_shift = 8,

--- 93 unchanged lines hidden (view full) ---

1700 .freq_table = pll_e_freq_table,
1701 .flags = TEGRA_PLL_FIXED | TEGRA_PLL_LOCK_MISC | TEGRA_PLL_USE_LOCK |
1702 TEGRA_PLL_HAS_LOCK_ENABLE,
1703 .fixed_rate = 100000000,
1704 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1705};
1706
1707static struct tegra_clk_pll_freq_table pll_re_vco_freq_table[] = {
1708 { 12000000, 672000000, 56, 1, 0, 0 },
1709 { 13000000, 672000000, 51, 1, 0, 0 }, /* actual: 663.0 MHz */
1710 { 38400000, 672000000, 70, 4, 0, 0 },
1708 { 12000000, 672000000, 56, 1, 1, 0 },
1709 { 13000000, 672000000, 51, 1, 1, 0 }, /* actual: 663.0 MHz */
1710 { 38400000, 672000000, 70, 4, 1, 0 },
1711 { 0, 0, 0, 0, 0, 0 },
1712};
1713
1714static struct div_nmp pllre_nmp = {
1715 .divm_shift = 0,
1716 .divm_width = 8,
1717 .divn_shift = 8,
1718 .divn_width = 8,

--- 30 unchanged lines hidden (view full) ---

1749 .divm_width = 8,
1750 .divn_shift = 10,
1751 .divn_width = 8,
1752 .divp_shift = 20,
1753 .divp_width = 5,
1754};
1755
1756static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1711 { 0, 0, 0, 0, 0, 0 },
1712};
1713
1714static struct div_nmp pllre_nmp = {
1715 .divm_shift = 0,
1716 .divm_width = 8,
1717 .divn_shift = 8,
1718 .divn_width = 8,

--- 30 unchanged lines hidden (view full) ---

1749 .divm_width = 8,
1750 .divn_shift = 10,
1751 .divn_width = 8,
1752 .divp_shift = 20,
1753 .divp_width = 5,
1754};
1755
1756static struct tegra_clk_pll_freq_table pll_p_freq_table[] = {
1757 { 12000000, 408000000, 34, 1, 0, 0 },
1758 { 38400000, 408000000, 85, 8, 0, 0 }, /* cf = 4.8MHz, allowed exception */
1757 { 12000000, 408000000, 34, 1, 1, 0 },
1758 { 38400000, 408000000, 85, 8, 1, 0 }, /* cf = 4.8MHz, allowed exception */
1759 { 0, 0, 0, 0, 0, 0 },
1760};
1761
1762static struct tegra_clk_pll_params pll_p_params = {
1763 .input_min = 9600000,
1764 .input_max = 800000000,
1765 .cf_min = 9600000,
1766 .cf_max = 19200000,

--- 48 unchanged lines hidden (view full) ---

1815 .divm_width = 8,
1816 .divn_shift = 8,
1817 .divn_width = 8,
1818 .divp_shift = 20,
1819 .divp_width = 5,
1820};
1821
1822static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
1759 { 0, 0, 0, 0, 0, 0 },
1760};
1761
1762static struct tegra_clk_pll_params pll_p_params = {
1763 .input_min = 9600000,
1764 .input_max = 800000000,
1765 .cf_min = 9600000,
1766 .cf_max = 19200000,

--- 48 unchanged lines hidden (view full) ---

1815 .divm_width = 8,
1816 .divn_shift = 8,
1817 .divn_width = 8,
1818 .divp_shift = 20,
1819 .divp_width = 5,
1820};
1821
1822static struct tegra_clk_pll_freq_table pll_a_freq_table[] = {
1823 { 12000000, 282240000, 47, 1, 1, 1, 0xf148 }, /* actual: 282240234 */
1824 { 12000000, 368640000, 61, 1, 1, 1, 0xfe15 }, /* actual: 368640381 */
1825 { 12000000, 240000000, 60, 1, 2, 1, 0 },
1826 { 13000000, 282240000, 43, 1, 1, 1, 0xfd7d }, /* actual: 282239807 */
1827 { 13000000, 368640000, 56, 1, 1, 1, 0x06d8 }, /* actual: 368640137 */
1828 { 13000000, 240000000, 55, 1, 2, 1, 0 }, /* actual: 238.3 MHz */
1829 { 38400000, 282240000, 44, 3, 1, 1, 0xf333 }, /* actual: 282239844 */
1830 { 38400000, 368640000, 57, 3, 1, 1, 0x0333 }, /* actual: 368639844 */
1823 { 12000000, 282240000, 47, 1, 2, 1, 0xf148 }, /* actual: 282240234 */
1824 { 12000000, 368640000, 61, 1, 2, 1, 0xfe15 }, /* actual: 368640381 */
1825 { 12000000, 240000000, 60, 1, 3, 1, 0 },
1826 { 13000000, 282240000, 43, 1, 2, 1, 0xfd7d }, /* actual: 282239807 */
1827 { 13000000, 368640000, 56, 1, 2, 1, 0x06d8 }, /* actual: 368640137 */
1828 { 13000000, 240000000, 55, 1, 3, 1, 0 }, /* actual: 238.3 MHz */
1829 { 38400000, 282240000, 44, 3, 2, 1, 0xf333 }, /* actual: 282239844 */
1830 { 38400000, 368640000, 57, 3, 2, 1, 0x0333 }, /* actual: 368639844 */
1831 { 38400000, 240000000, 75, 3, 3, 1, 0 },
1832 { 0, 0, 0, 0, 0, 0, 0 },
1833};
1834
1835static struct tegra_clk_pll_params pll_a_params = {
1836 .input_min = 12000000,
1837 .input_max = 800000000,
1838 .cf_min = 12000000,

--- 29 unchanged lines hidden (view full) ---

1868 .divm_width = 8,
1869 .divn_shift = 11,
1870 .divn_width = 8,
1871 .divp_shift = 20,
1872 .divp_width = 3,
1873};
1874
1875static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
1831 { 38400000, 240000000, 75, 3, 3, 1, 0 },
1832 { 0, 0, 0, 0, 0, 0, 0 },
1833};
1834
1835static struct tegra_clk_pll_params pll_a_params = {
1836 .input_min = 12000000,
1837 .input_max = 800000000,
1838 .cf_min = 12000000,

--- 29 unchanged lines hidden (view full) ---

1868 .divm_width = 8,
1869 .divn_shift = 11,
1870 .divn_width = 8,
1871 .divp_shift = 20,
1872 .divp_width = 3,
1873};
1874
1875static struct tegra_clk_pll_freq_table pll_d_freq_table[] = {
1876 { 12000000, 594000000, 99, 1, 1, 0, 0 },
1877 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1878 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1876 { 12000000, 594000000, 99, 1, 2, 0, 0 },
1877 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
1878 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
1879 { 0, 0, 0, 0, 0, 0, 0 },
1880};
1881
1882static struct tegra_clk_pll_params pll_d_params = {
1883 .input_min = 12000000,
1884 .input_max = 800000000,
1885 .cf_min = 12000000,
1886 .cf_max = 38400000,

--- 19 unchanged lines hidden (view full) ---

1906 .mdiv_default = 1,
1907 .set_defaults = tegra210_plld_set_defaults,
1908 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1909 .set_gain = tegra210_clk_pll_set_gain,
1910 .adjust_vco = tegra210_clk_adjust_vco_min,
1911};
1912
1913static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
1879 { 0, 0, 0, 0, 0, 0, 0 },
1880};
1881
1882static struct tegra_clk_pll_params pll_d_params = {
1883 .input_min = 12000000,
1884 .input_max = 800000000,
1885 .cf_min = 12000000,
1886 .cf_max = 38400000,

--- 19 unchanged lines hidden (view full) ---

1906 .mdiv_default = 1,
1907 .set_defaults = tegra210_plld_set_defaults,
1908 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1909 .set_gain = tegra210_clk_pll_set_gain,
1910 .adjust_vco = tegra210_clk_adjust_vco_min,
1911};
1912
1913static struct tegra_clk_pll_freq_table tegra210_pll_d2_freq_table[] = {
1914 { 12000000, 594000000, 99, 1, 1, 0, 0xf000 },
1915 { 13000000, 594000000, 91, 1, 1, 0, 0xfc4f }, /* actual: 594000183 */
1916 { 38400000, 594000000, 30, 1, 1, 0, 0x0e00 },
1914 { 12000000, 594000000, 99, 1, 2, 0, 0xf000 },
1915 { 13000000, 594000000, 91, 1, 2, 0, 0xfc4f }, /* actual: 594000183 */
1916 { 38400000, 594000000, 30, 1, 2, 0, 0x0e00 },
1917 { 0, 0, 0, 0, 0, 0, 0 },
1918};
1919
1920/* s/w policy, always tegra_pll_ref */
1921static struct tegra_clk_pll_params pll_d2_params = {
1922 .input_min = 12000000,
1923 .input_max = 800000000,
1924 .cf_min = 12000000,

--- 5 unchanged lines hidden (view full) ---

1930 .lock_mask = PLL_BASE_LOCK,
1931 .lock_delay = 300,
1932 .iddq_reg = PLLD2_BASE,
1933 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1934 .sdm_din_reg = PLLD2_MISC3,
1935 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1936 .sdm_ctrl_reg = PLLD2_MISC1,
1937 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
1917 { 0, 0, 0, 0, 0, 0, 0 },
1918};
1919
1920/* s/w policy, always tegra_pll_ref */
1921static struct tegra_clk_pll_params pll_d2_params = {
1922 .input_min = 12000000,
1923 .input_max = 800000000,
1924 .cf_min = 12000000,

--- 5 unchanged lines hidden (view full) ---

1930 .lock_mask = PLL_BASE_LOCK,
1931 .lock_delay = 300,
1932 .iddq_reg = PLLD2_BASE,
1933 .iddq_bit_idx = PLLSS_IDDQ_BIT,
1934 .sdm_din_reg = PLLD2_MISC3,
1935 .sdm_din_mask = PLLA_SDM_DIN_MASK,
1936 .sdm_ctrl_reg = PLLD2_MISC1,
1937 .sdm_ctrl_en_mask = PLLD2_SDM_EN_MASK,
1938 .ssc_ctrl_reg = PLLD2_MISC1,
1939 .ssc_ctrl_en_mask = PLLD2_SSC_EN_MASK,
1938 /* disable spread-spectrum for pll_d2 */
1939 .ssc_ctrl_reg = 0,
1940 .ssc_ctrl_en_mask = 0,
1940 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1941 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1942 .div_nmp = &pllss_nmp,
1943 .ext_misc_reg[0] = PLLD2_MISC0,
1944 .ext_misc_reg[1] = PLLD2_MISC1,
1945 .ext_misc_reg[2] = PLLD2_MISC2,
1946 .ext_misc_reg[3] = PLLD2_MISC3,
1947 .max_p = PLL_QLIN_PDIV_MAX,
1948 .mdiv_default = 1,
1949 .freq_table = tegra210_pll_d2_freq_table,
1950 .set_defaults = tegra210_plld2_set_defaults,
1951 .flags = TEGRA_PLL_USE_LOCK,
1952 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1953 .set_gain = tegra210_clk_pll_set_gain,
1954 .adjust_vco = tegra210_clk_adjust_vco_min,
1955};
1956
1957static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
1941 .round_p_to_pdiv = pll_qlin_p_to_pdiv,
1942 .pdiv_tohw = pll_qlin_pdiv_to_hw,
1943 .div_nmp = &pllss_nmp,
1944 .ext_misc_reg[0] = PLLD2_MISC0,
1945 .ext_misc_reg[1] = PLLD2_MISC1,
1946 .ext_misc_reg[2] = PLLD2_MISC2,
1947 .ext_misc_reg[3] = PLLD2_MISC3,
1948 .max_p = PLL_QLIN_PDIV_MAX,
1949 .mdiv_default = 1,
1950 .freq_table = tegra210_pll_d2_freq_table,
1951 .set_defaults = tegra210_plld2_set_defaults,
1952 .flags = TEGRA_PLL_USE_LOCK,
1953 .calc_rate = tegra210_pll_fixed_mdiv_cfg,
1954 .set_gain = tegra210_clk_pll_set_gain,
1955 .adjust_vco = tegra210_clk_adjust_vco_min,
1956};
1957
1958static struct tegra_clk_pll_freq_table pll_dp_freq_table[] = {
1958 { 12000000, 270000000, 90, 1, 3, 0, 0xf000 },
1959 { 13000000, 270000000, 83, 1, 3, 0, 0xf000 }, /* actual: 269.8 MHz */
1960 { 38400000, 270000000, 28, 1, 3, 0, 0xf400 },
1959 { 12000000, 270000000, 90, 1, 4, 0, 0xf000 },
1960 { 13000000, 270000000, 83, 1, 4, 0, 0xf000 }, /* actual: 269.8 MHz */
1961 { 38400000, 270000000, 28, 1, 4, 0, 0xf400 },
1961 { 0, 0, 0, 0, 0, 0, 0 },
1962};
1963
1964static struct tegra_clk_pll_params pll_dp_params = {
1965 .input_min = 12000000,
1966 .input_max = 800000000,
1967 .cf_min = 12000000,
1968 .cf_max = 38400000,

--- 33 unchanged lines hidden (view full) ---

2002 .divm_width = 8,
2003 .divn_shift = 8,
2004 .divn_width = 8,
2005 .divp_shift = 16,
2006 .divp_width = 5,
2007};
2008
2009static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
1962 { 0, 0, 0, 0, 0, 0, 0 },
1963};
1964
1965static struct tegra_clk_pll_params pll_dp_params = {
1966 .input_min = 12000000,
1967 .input_max = 800000000,
1968 .cf_min = 12000000,
1969 .cf_max = 38400000,

--- 33 unchanged lines hidden (view full) ---

2003 .divm_width = 8,
2004 .divn_shift = 8,
2005 .divn_width = 8,
2006 .divp_shift = 16,
2007 .divp_width = 5,
2008};
2009
2010static struct tegra_clk_pll_freq_table pll_u_freq_table[] = {
2010 { 12000000, 480000000, 40, 1, 0, 0 },
2011 { 13000000, 480000000, 36, 1, 0, 0 }, /* actual: 468.0 MHz */
2012 { 38400000, 480000000, 25, 2, 0, 0 },
2011 { 12000000, 480000000, 40, 1, 1, 0 },
2012 { 13000000, 480000000, 36, 1, 1, 0 }, /* actual: 468.0 MHz */
2013 { 38400000, 480000000, 25, 2, 1, 0 },
2013 { 0, 0, 0, 0, 0, 0 },
2014};
2015
2016static struct tegra_clk_pll_params pll_u_vco_params = {
2017 .input_min = 9600000,
2018 .input_max = 800000000,
2019 .cf_min = 9600000,
2020 .cf_max = 19200000,

--- 128 unchanged lines hidden (view full) ---

2149 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2150 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2151 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2152 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2153 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2154 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
2155 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2156 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2014 { 0, 0, 0, 0, 0, 0 },
2015};
2016
2017static struct tegra_clk_pll_params pll_u_vco_params = {
2018 .input_min = 9600000,
2019 .input_max = 800000000,
2020 .cf_min = 9600000,
2021 .cf_max = 19200000,

--- 128 unchanged lines hidden (view full) ---

2150 [tegra_clk_i2c6] = { .dt_id = TEGRA210_CLK_I2C6, .present = true },
2151 [tegra_clk_vim2_clk] = { .dt_id = TEGRA210_CLK_VIM2_CLK, .present = true },
2152 [tegra_clk_clk72Mhz_8] = { .dt_id = TEGRA210_CLK_CLK72MHZ, .present = true },
2153 [tegra_clk_vic03_8] = { .dt_id = TEGRA210_CLK_VIC03, .present = true },
2154 [tegra_clk_dpaux] = { .dt_id = TEGRA210_CLK_DPAUX, .present = true },
2155 [tegra_clk_dpaux1] = { .dt_id = TEGRA210_CLK_DPAUX1, .present = true },
2156 [tegra_clk_sor0] = { .dt_id = TEGRA210_CLK_SOR0, .present = true },
2157 [tegra_clk_sor0_lvds] = { .dt_id = TEGRA210_CLK_SOR0_LVDS, .present = true },
2158 [tegra_clk_sor1] = { .dt_id = TEGRA210_CLK_SOR1, .present = true },
2159 [tegra_clk_sor1_src] = { .dt_id = TEGRA210_CLK_SOR1_SRC, .present = true },
2157 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2158 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2159 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2160 [tegra_clk_vfir] = { .dt_id = TEGRA210_CLK_VFIR, .present = true },
2161 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2162 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2163 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2164 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },

--- 293 unchanged lines hidden (view full) ---

2458{
2459 struct clk *clk;
2460
2461 /* xusb_ss_div2 */
2462 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
2463 1, 2);
2464 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
2465
2160 [tegra_clk_gpu] = { .dt_id = TEGRA210_CLK_GPU, .present = true },
2161 [tegra_clk_pll_g_ref] = { .dt_id = TEGRA210_CLK_PLL_G_REF, .present = true, },
2162 [tegra_clk_uartb_8] = { .dt_id = TEGRA210_CLK_UARTB, .present = true },
2163 [tegra_clk_vfir] = { .dt_id = TEGRA210_CLK_VFIR, .present = true },
2164 [tegra_clk_spdif_in_8] = { .dt_id = TEGRA210_CLK_SPDIF_IN, .present = true },
2165 [tegra_clk_spdif_out] = { .dt_id = TEGRA210_CLK_SPDIF_OUT, .present = true },
2166 [tegra_clk_vi_10] = { .dt_id = TEGRA210_CLK_VI, .present = true },
2167 [tegra_clk_vi_sensor_8] = { .dt_id = TEGRA210_CLK_VI_SENSOR, .present = true },

--- 293 unchanged lines hidden (view full) ---

2461{
2462 struct clk *clk;
2463
2464 /* xusb_ss_div2 */
2465 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0,
2466 1, 2);
2467 clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk;
2468
2466 clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base,
2469 clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base,
2467 1, 17, 181);
2468 clks[TEGRA210_CLK_DPAUX] = clk;
2469
2470 1, 17, 181);
2471 clks[TEGRA210_CLK_DPAUX] = clk;
2472
2470 clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base,
2473 clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base,
2471 1, 17, 207);
2472 clks[TEGRA210_CLK_DPAUX1] = clk;
2473
2474 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
2475 1, 17, 222);
2476 clks[TEGRA210_CLK_SOR_SAFE] = clk;
2477
2478 /* pll_d_dsi_out */

--- 445 unchanged lines hidden ---
2474 1, 17, 207);
2475 clks[TEGRA210_CLK_DPAUX1] = clk;
2476
2477 clk = tegra_clk_register_periph_fixed("sor_safe", "pll_p", 0, clk_base,
2478 1, 17, 222);
2479 clks[TEGRA210_CLK_SOR_SAFE] = clk;
2480
2481 /* pll_d_dsi_out */

--- 445 unchanged lines hidden ---