clk-tegra210.c (5f675231e456cb599b283f8361f01cf34b0617df) clk-tegra210.c (845d782d91448e0fbca686bca2cc9f9c2a9ba3e7)
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

--- 3356 unchanged lines hidden (view full) ---

3365 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3366 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3367 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3368 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
3369 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3370 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3371 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
3372 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
1/*
2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

--- 3356 unchanged lines hidden (view full) ---

3365 { TEGRA210_CLK_I2C4, TEGRA210_CLK_PLL_P, 0, 0 },
3366 { TEGRA210_CLK_I2C5, TEGRA210_CLK_PLL_P, 0, 0 },
3367 { TEGRA210_CLK_I2C6, TEGRA210_CLK_PLL_P, 0, 0 },
3368 { TEGRA210_CLK_PLL_DP, TEGRA210_CLK_CLK_MAX, 270000000, 0 },
3369 { TEGRA210_CLK_SOC_THERM, TEGRA210_CLK_PLL_P, 51000000, 0 },
3370 { TEGRA210_CLK_CCLK_G, TEGRA210_CLK_CLK_MAX, 0, 1 },
3371 { TEGRA210_CLK_PLL_U_OUT1, TEGRA210_CLK_CLK_MAX, 48000000, 1 },
3372 { TEGRA210_CLK_PLL_U_OUT2, TEGRA210_CLK_CLK_MAX, 60000000, 1 },
3373 { TEGRA210_CLK_SPDIF_IN_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3374 { TEGRA210_CLK_I2S0_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3375 { TEGRA210_CLK_I2S1_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3376 { TEGRA210_CLK_I2S2_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3377 { TEGRA210_CLK_I2S3_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3378 { TEGRA210_CLK_I2S4_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3379 { TEGRA210_CLK_VIMCLK_SYNC, TEGRA210_CLK_CLK_MAX, 24576000, 0 },
3373 /* This MUST be the last entry. */
3374 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3375};
3376
3377/**
3378 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
3379 *
3380 * Program an initial clock rate and enable or disable clocks needed

--- 177 unchanged lines hidden (view full) ---

3558 &osc_freq, &pll_ref_freq) < 0)
3559 return;
3560
3561 tegra_fixed_clk_init(tegra210_clks);
3562 tegra210_pll_init(clk_base, pmc_base);
3563 tegra210_periph_clk_init(clk_base, pmc_base);
3564 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3565 tegra210_audio_plls,
3380 /* This MUST be the last entry. */
3381 { TEGRA210_CLK_CLK_MAX, TEGRA210_CLK_CLK_MAX, 0, 0 },
3382};
3383
3384/**
3385 * tegra210_clock_apply_init_table - initialize clocks on Tegra210 SoCs
3386 *
3387 * Program an initial clock rate and enable or disable clocks needed

--- 177 unchanged lines hidden (view full) ---

3565 &osc_freq, &pll_ref_freq) < 0)
3566 return;
3567
3568 tegra_fixed_clk_init(tegra210_clks);
3569 tegra210_pll_init(clk_base, pmc_base);
3570 tegra210_periph_clk_init(clk_base, pmc_base);
3571 tegra_audio_clk_init(clk_base, pmc_base, tegra210_clks,
3572 tegra210_audio_plls,
3566 ARRAY_SIZE(tegra210_audio_plls));
3573 ARRAY_SIZE(tegra210_audio_plls), 24576000);
3567 tegra_pmc_clk_init(pmc_base, tegra210_clks);
3568
3569 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
3570 value = clk_readl(clk_base + PLLD_BASE);
3571 value &= ~BIT(25);
3572 clk_writel(value, clk_base + PLLD_BASE);
3573
3574 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;

--- 14 unchanged lines hidden ---
3574 tegra_pmc_clk_init(pmc_base, tegra210_clks);
3575
3576 /* For Tegra210, PLLD is the only source for DSIA & DSIB */
3577 value = clk_readl(clk_base + PLLD_BASE);
3578 value &= ~BIT(25);
3579 clk_writel(value, clk_base + PLLD_BASE);
3580
3581 tegra_clk_apply_init_table = tegra210_clock_apply_init_table;

--- 14 unchanged lines hidden ---