clk-tegra210.c (10a558374f3751cf4eb55143008975641dfc2cf4) | clk-tegra210.c (89e423c3f14c4a87d124e4a5437dc337b90b6f29) |
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1/* 2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 27 unchanged lines hidden (view full) --- 36 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See 37 * periph_regs[] in drivers/clk/tegra/clk.c 38 */ 39#define TEGRA210_CAR_BANK_COUNT 7 40 41#define CLK_SOURCE_CSITE 0x1d4 42#define CLK_SOURCE_EMC 0x19c 43#define CLK_SOURCE_SOR1 0x410 | 1/* 2 * Copyright (c) 2012-2014 NVIDIA CORPORATION. All rights reserved. 3 * 4 * This program is free software; you can redistribute it and/or modify it 5 * under the terms and conditions of the GNU General Public License, 6 * version 2, as published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope it will be useful, but WITHOUT --- 27 unchanged lines hidden (view full) --- 36 * identified by single letters, e.g.: L, H, U, V, W, X, Y. See 37 * periph_regs[] in drivers/clk/tegra/clk.c 38 */ 39#define TEGRA210_CAR_BANK_COUNT 7 40 41#define CLK_SOURCE_CSITE 0x1d4 42#define CLK_SOURCE_EMC 0x19c 43#define CLK_SOURCE_SOR1 0x410 |
44#define CLK_SOURCE_LA 0x1f8 |
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44 45#define PLLC_BASE 0x80 46#define PLLC_OUT 0x84 47#define PLLC_MISC0 0x88 48#define PLLC_MISC1 0x8c 49#define PLLC_MISC2 0x5d0 50#define PLLC_MISC3 0x5d4 51 --- 2597 unchanged lines hidden (view full) --- 2649 2650static struct tegra_periph_init_data tegra210_periph[] = { 2651 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents, 2652 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1, 2653 TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1, 2654 sor1_parents_idx, 0, &sor1_lock), 2655}; 2656 | 45 46#define PLLC_BASE 0x80 47#define PLLC_OUT 0x84 48#define PLLC_MISC0 0x88 49#define PLLC_MISC1 0x8c 50#define PLLC_MISC2 0x5d0 51#define PLLC_MISC3 0x5d4 52 --- 2597 unchanged lines hidden (view full) --- 2650 2651static struct tegra_periph_init_data tegra210_periph[] = { 2652 TEGRA_INIT_DATA_TABLE("sor1", NULL, NULL, sor1_parents, 2653 CLK_SOURCE_SOR1, 29, 0x7, 0, 0, 8, 1, 2654 TEGRA_DIVIDER_ROUND_UP, 183, 0, tegra_clk_sor1, 2655 sor1_parents_idx, 0, &sor1_lock), 2656}; 2657 |
2658static const char * const la_parents[] = { 2659 "pll_p", "pll_c2", "pll_c", "pll_c3", "pll_re_out1", "pll_a1", "clk_m", "pll_c4_out0" 2660}; 2661 2662static struct tegra_clk_periph tegra210_la = 2663 TEGRA_CLK_PERIPH(29, 7, 9, 0, 8, 1, TEGRA_DIVIDER_ROUND_UP, 76, 0, NULL, 0); 2664 |
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2657static __init void tegra210_periph_clk_init(void __iomem *clk_base, 2658 void __iomem *pmc_base) 2659{ 2660 struct clk *clk; 2661 unsigned int i; 2662 2663 /* xusb_ss_div2 */ 2664 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, --- 30 unchanged lines hidden (view full) --- 2695 clks[TEGRA210_CLK_DSIA] = clk; 2696 2697 /* dsib */ 2698 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, 2699 clk_base, 0, 82, 2700 periph_clk_enb_refcnt); 2701 clks[TEGRA210_CLK_DSIB] = clk; 2702 | 2665static __init void tegra210_periph_clk_init(void __iomem *clk_base, 2666 void __iomem *pmc_base) 2667{ 2668 struct clk *clk; 2669 unsigned int i; 2670 2671 /* xusb_ss_div2 */ 2672 clk = clk_register_fixed_factor(NULL, "xusb_ss_div2", "xusb_ss_src", 0, --- 30 unchanged lines hidden (view full) --- 2703 clks[TEGRA210_CLK_DSIA] = clk; 2704 2705 /* dsib */ 2706 clk = tegra_clk_register_periph_gate("dsib", "pll_d_dsi_out", 0, 2707 clk_base, 0, 82, 2708 periph_clk_enb_refcnt); 2709 clks[TEGRA210_CLK_DSIB] = clk; 2710 |
2711 /* la */ 2712 clk = tegra_clk_register_periph("la", la_parents, 2713 ARRAY_SIZE(la_parents), &tegra210_la, clk_base, 2714 CLK_SOURCE_LA, 0); 2715 clks[TEGRA210_CLK_LA] = clk; 2716 |
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2703 /* emc mux */ 2704 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2705 ARRAY_SIZE(mux_pllmcp_clkm), 0, 2706 clk_base + CLK_SOURCE_EMC, 2707 29, 3, 0, &emc_lock); 2708 2709 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, 2710 &emc_lock); --- 514 unchanged lines hidden --- | 2717 /* emc mux */ 2718 clk = clk_register_mux(NULL, "emc_mux", mux_pllmcp_clkm, 2719 ARRAY_SIZE(mux_pllmcp_clkm), 0, 2720 clk_base + CLK_SOURCE_EMC, 2721 29, 3, 0, &emc_lock); 2722 2723 clk = tegra_clk_register_mc("mc", "emc_mux", clk_base + CLK_SOURCE_EMC, 2724 &emc_lock); --- 514 unchanged lines hidden --- |