clk-tegra114.c (415d2b3392d7a80903e0f97f051201aa02bf20e9) clk-tegra114.c (845d782d91448e0fbca686bca2cc9f9c2a9ba3e7)
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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1185 { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1186 { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
1187 { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
1188 { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
1189 { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
1190 { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
1191 { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1192 { TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
1/*
2 * Copyright (c) 2012, 2013, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT

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1185 { TEGRA114_CLK_DSIBLP, TEGRA114_CLK_PLL_P, 68000000, 0 },
1186 { TEGRA114_CLK_PLL_RE_VCO, TEGRA114_CLK_CLK_MAX, 612000000, 0 },
1187 { TEGRA114_CLK_XUSB_SS_SRC, TEGRA114_CLK_PLL_RE_OUT, 122400000, 0 },
1188 { TEGRA114_CLK_XUSB_FS_SRC, TEGRA114_CLK_PLL_U_48M, 48000000, 0 },
1189 { TEGRA114_CLK_XUSB_HS_SRC, TEGRA114_CLK_XUSB_SS_DIV2, 61200000, 0 },
1190 { TEGRA114_CLK_XUSB_FALCON_SRC, TEGRA114_CLK_PLL_P, 204000000, 0 },
1191 { TEGRA114_CLK_XUSB_HOST_SRC, TEGRA114_CLK_PLL_P, 102000000, 0 },
1192 { TEGRA114_CLK_VDE, TEGRA114_CLK_CLK_MAX, 600000000, 0 },
1193 { TEGRA114_CLK_SPDIF_IN_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1194 { TEGRA114_CLK_I2S0_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1195 { TEGRA114_CLK_I2S1_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1196 { TEGRA114_CLK_I2S2_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1197 { TEGRA114_CLK_I2S3_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1198 { TEGRA114_CLK_I2S4_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1199 { TEGRA114_CLK_VIMCLK_SYNC, TEGRA114_CLK_CLK_MAX, 24000000, 0 },
1193 /* must be the last entry */
1194 { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
1195};
1196
1197static void __init tegra114_clock_apply_init_table(void)
1198{
1199 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
1200}

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1357 &pll_ref_freq) < 0)
1358 return;
1359
1360 tegra114_fixed_clk_init(clk_base);
1361 tegra114_pll_init(clk_base, pmc_base);
1362 tegra114_periph_clk_init(clk_base, pmc_base);
1363 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
1364 tegra114_audio_plls,
1200 /* must be the last entry */
1201 { TEGRA114_CLK_CLK_MAX, TEGRA114_CLK_CLK_MAX, 0, 0 },
1202};
1203
1204static void __init tegra114_clock_apply_init_table(void)
1205{
1206 tegra_init_from_table(init_table, clks, TEGRA114_CLK_CLK_MAX);
1207}

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1364 &pll_ref_freq) < 0)
1365 return;
1366
1367 tegra114_fixed_clk_init(clk_base);
1368 tegra114_pll_init(clk_base, pmc_base);
1369 tegra114_periph_clk_init(clk_base, pmc_base);
1370 tegra_audio_clk_init(clk_base, pmc_base, tegra114_clks,
1371 tegra114_audio_plls,
1365 ARRAY_SIZE(tegra114_audio_plls));
1372 ARRAY_SIZE(tegra114_audio_plls), 24000000);
1366 tegra_pmc_clk_init(pmc_base, tegra114_clks);
1367 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1368 &pll_x_params);
1369
1370 tegra_add_of_provider(np, of_clk_src_onecell_get);
1371 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1372
1373 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1374
1375 tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1376}
1377CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);
1373 tegra_pmc_clk_init(pmc_base, tegra114_clks);
1374 tegra_super_clk_gen4_init(clk_base, pmc_base, tegra114_clks,
1375 &pll_x_params);
1376
1377 tegra_add_of_provider(np, of_clk_src_onecell_get);
1378 tegra_register_devclks(devclks, ARRAY_SIZE(devclks));
1379
1380 tegra_clk_apply_init_table = tegra114_clock_apply_init_table;
1381
1382 tegra_cpu_car_ops = &tegra114_cpu_car_ops;
1383}
1384CLK_OF_DECLARE(tegra114, "nvidia,tegra114-car", tegra114_clock_init);