clkgen-mux.c (b10778a00d40b3d9fdaaf5891e802794781ff71c) clkgen-mux.c (4e907ef6bd5eeb18bcc78f08bc993b94f007b79f)
1/*
2 * clkgen-mux.c: ST GEN-MUX Clock driver
3 *
4 * Copyright (C) 2014 STMicroelectronics (R&D) Limited
5 *
6 * Authors: Stephen Gallimore <stephen.gallimore@st.com>
7 * Pankaj Dev <pankaj.dev@st.com>
8 *

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89
90static int clkgena_divmux_enable(struct clk_hw *hw)
91{
92 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
93 struct clk_hw *mux_hw = &genamux->mux.hw;
94 unsigned long timeout;
95 int ret = 0;
96
1/*
2 * clkgen-mux.c: ST GEN-MUX Clock driver
3 *
4 * Copyright (C) 2014 STMicroelectronics (R&D) Limited
5 *
6 * Authors: Stephen Gallimore <stephen.gallimore@st.com>
7 * Pankaj Dev <pankaj.dev@st.com>
8 *

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89
90static int clkgena_divmux_enable(struct clk_hw *hw)
91{
92 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
93 struct clk_hw *mux_hw = &genamux->mux.hw;
94 unsigned long timeout;
95 int ret = 0;
96
97 mux_hw->clk = hw->clk;
97 __clk_hw_set_clk(mux_hw, hw);
98
99 ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);
100 if (ret)
101 return ret;
102
103 timeout = jiffies + msecs_to_jiffies(10);
104
105 while (!clkgena_divmux_is_running(genamux)) {

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111 return 0;
112}
113
114static void clkgena_divmux_disable(struct clk_hw *hw)
115{
116 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
117 struct clk_hw *mux_hw = &genamux->mux.hw;
118
98
99 ret = clk_mux_ops.set_parent(mux_hw, genamux->muxsel);
100 if (ret)
101 return ret;
102
103 timeout = jiffies + msecs_to_jiffies(10);
104
105 while (!clkgena_divmux_is_running(genamux)) {

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111 return 0;
112}
113
114static void clkgena_divmux_disable(struct clk_hw *hw)
115{
116 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
117 struct clk_hw *mux_hw = &genamux->mux.hw;
118
119 mux_hw->clk = hw->clk;
119 __clk_hw_set_clk(mux_hw, hw);
120
121 clk_mux_ops.set_parent(mux_hw, CKGAX_CLKOPSRC_SWITCH_OFF);
122}
123
124static int clkgena_divmux_is_enabled(struct clk_hw *hw)
125{
126 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
127 struct clk_hw *mux_hw = &genamux->mux.hw;
128
120
121 clk_mux_ops.set_parent(mux_hw, CKGAX_CLKOPSRC_SWITCH_OFF);
122}
123
124static int clkgena_divmux_is_enabled(struct clk_hw *hw)
125{
126 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
127 struct clk_hw *mux_hw = &genamux->mux.hw;
128
129 mux_hw->clk = hw->clk;
129 __clk_hw_set_clk(mux_hw, hw);
130
131 return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
132}
133
134u8 clkgena_divmux_get_parent(struct clk_hw *hw)
135{
136 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
137 struct clk_hw *mux_hw = &genamux->mux.hw;
138
130
131 return (s8)clk_mux_ops.get_parent(mux_hw) > 0;
132}
133
134u8 clkgena_divmux_get_parent(struct clk_hw *hw)
135{
136 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
137 struct clk_hw *mux_hw = &genamux->mux.hw;
138
139 mux_hw->clk = hw->clk;
139 __clk_hw_set_clk(mux_hw, hw);
140
141 genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
142 if ((s8)genamux->muxsel < 0) {
143 pr_debug("%s: %s: Invalid parent, setting to default.\n",
144 __func__, __clk_get_name(hw->clk));
145 genamux->muxsel = 0;
146 }
147

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169}
170
171unsigned long clkgena_divmux_recalc_rate(struct clk_hw *hw,
172 unsigned long parent_rate)
173{
174 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
175 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
176
140
141 genamux->muxsel = clk_mux_ops.get_parent(mux_hw);
142 if ((s8)genamux->muxsel < 0) {
143 pr_debug("%s: %s: Invalid parent, setting to default.\n",
144 __func__, __clk_get_name(hw->clk));
145 genamux->muxsel = 0;
146 }
147

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169}
170
171unsigned long clkgena_divmux_recalc_rate(struct clk_hw *hw,
172 unsigned long parent_rate)
173{
174 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
175 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
176
177 div_hw->clk = hw->clk;
177 __clk_hw_set_clk(div_hw, hw);
178
179 return clk_divider_ops.recalc_rate(div_hw, parent_rate);
180}
181
182static int clkgena_divmux_set_rate(struct clk_hw *hw, unsigned long rate,
183 unsigned long parent_rate)
184{
185 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
186 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
187
178
179 return clk_divider_ops.recalc_rate(div_hw, parent_rate);
180}
181
182static int clkgena_divmux_set_rate(struct clk_hw *hw, unsigned long rate,
183 unsigned long parent_rate)
184{
185 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
186 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
187
188 div_hw->clk = hw->clk;
188 __clk_hw_set_clk(div_hw, hw);
189
190 return clk_divider_ops.set_rate(div_hw, rate, parent_rate);
191}
192
193static long clkgena_divmux_round_rate(struct clk_hw *hw, unsigned long rate,
194 unsigned long *prate)
195{
196 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
197 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
198
189
190 return clk_divider_ops.set_rate(div_hw, rate, parent_rate);
191}
192
193static long clkgena_divmux_round_rate(struct clk_hw *hw, unsigned long rate,
194 unsigned long *prate)
195{
196 struct clkgena_divmux *genamux = to_clkgena_divmux(hw);
197 struct clk_hw *div_hw = &genamux->div[genamux->muxsel].hw;
198
199 div_hw->clk = hw->clk;
199 __clk_hw_set_clk(div_hw, hw);
200
201 return clk_divider_ops.round_rate(div_hw, rate, prate);
202}
203
204static const struct clk_ops clkgena_divmux_ops = {
205 .enable = clkgena_divmux_enable,
206 .disable = clkgena_divmux_disable,
207 .is_enabled = clkgena_divmux_is_enabled,

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201 return clk_divider_ops.round_rate(div_hw, rate, prate);
202}
203
204static const struct clk_ops clkgena_divmux_ops = {
205 .enable = clkgena_divmux_enable,
206 .disable = clkgena_divmux_disable,
207 .is_enabled = clkgena_divmux_is_enabled,

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