clk.c (2871f352c600d36b1b8ba57c79029cf8aa512948) clk.c (b2155a71a7ff828eac72367ff9c2a0a2f4fec35b)
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * based on
6 *
7 * samsung/clk.c
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.

--- 89 unchanged lines hidden (view full) ---

98 mux ? &mux->hw : NULL, mux_ops,
99 div ? &div->hw : NULL, div_ops,
100 gate ? &gate->hw : NULL, gate_ops,
101 flags);
102
103 return clk;
104}
105
1/*
2 * Copyright (c) 2014 MundoReader S.L.
3 * Author: Heiko Stuebner <heiko@sntech.de>
4 *
5 * based on
6 *
7 * samsung/clk.c
8 * Copyright (c) 2013 Samsung Electronics Co., Ltd.

--- 89 unchanged lines hidden (view full) ---

98 mux ? &mux->hw : NULL, mux_ops,
99 div ? &div->hw : NULL, div_ops,
100 gate ? &gate->hw : NULL, gate_ops,
101 flags);
102
103 return clk;
104}
105
106static struct clk *rockchip_clk_register_frac_branch(const char *name,
107 const char **parent_names, u8 num_parents, void __iomem *base,
108 int muxdiv_offset, u8 div_flags,
109 int gate_offset, u8 gate_shift, u8 gate_flags,
110 unsigned long flags, spinlock_t *lock)
111{
112 struct clk *clk;
113 struct clk_gate *gate = NULL;
114 struct clk_fractional_divider *div = NULL;
115 const struct clk_ops *div_ops = NULL, *gate_ops = NULL;
116
117 if (gate_offset >= 0) {
118 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
119 if (!gate)
120 return ERR_PTR(-ENOMEM);
121
122 gate->flags = gate_flags;
123 gate->reg = base + gate_offset;
124 gate->bit_idx = gate_shift;
125 gate->lock = lock;
126 gate_ops = &clk_gate_ops;
127 }
128
129 if (muxdiv_offset < 0)
130 return ERR_PTR(-EINVAL);
131
132 div = kzalloc(sizeof(*div), GFP_KERNEL);
133 if (!div)
134 return ERR_PTR(-ENOMEM);
135
136 div->flags = div_flags;
137 div->reg = base + muxdiv_offset;
138 div->mshift = 16;
139 div->mmask = 0xffff0000;
140 div->nshift = 0;
141 div->nmask = 0xffff;
142 div->lock = lock;
143 div_ops = &clk_fractional_divider_ops;
144
145 clk = clk_register_composite(NULL, name, parent_names, num_parents,
146 NULL, NULL,
147 &div->hw, div_ops,
148 gate ? &gate->hw : NULL, gate_ops,
149 flags);
150
151 return clk;
152}
153
106static DEFINE_SPINLOCK(clk_lock);
107static struct clk **clk_table;
108static void __iomem *reg_base;
109static struct clk_onecell_data clk_data;
110static struct device_node *cru_node;
111static struct regmap *grf;
112
113void __init rockchip_clk_init(struct device_node *np, void __iomem *base,

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192 else
193 clk = clk_register_divider(NULL, list->name,
194 list->parent_names[0], flags,
195 reg_base + list->muxdiv_offset,
196 list->div_shift, list->div_width,
197 list->div_flags, &clk_lock);
198 break;
199 case branch_fraction_divider:
154static DEFINE_SPINLOCK(clk_lock);
155static struct clk **clk_table;
156static void __iomem *reg_base;
157static struct clk_onecell_data clk_data;
158static struct device_node *cru_node;
159static struct regmap *grf;
160
161void __init rockchip_clk_init(struct device_node *np, void __iomem *base,

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240 else
241 clk = clk_register_divider(NULL, list->name,
242 list->parent_names[0], flags,
243 reg_base + list->muxdiv_offset,
244 list->div_shift, list->div_width,
245 list->div_flags, &clk_lock);
246 break;
247 case branch_fraction_divider:
200 /* unimplemented */
201 continue;
248 /* keep all gates untouched for now */
249 flags |= CLK_IGNORE_UNUSED;
250
251 clk = rockchip_clk_register_frac_branch(list->name,
252 list->parent_names, list->num_parents,
253 reg_base, list->muxdiv_offset, list->div_flags,
254 list->gate_offset, list->gate_shift,
255 list->gate_flags, flags, &clk_lock);
202 break;
203 case branch_gate:
204 flags |= CLK_SET_RATE_PARENT;
205
206 /* keep all gates untouched for now */
207 flags |= CLK_IGNORE_UNUSED;
208
209 clk = clk_register_gate(NULL, list->name,

--- 35 unchanged lines hidden --- 		256 break;
257 case branch_gate:
258 flags |= CLK_SET_RATE_PARENT;
259
260 /* keep all gates untouched for now */
261 flags |= CLK_IGNORE_UNUSED;
262
263 clk = clk_register_gate(NULL, list->name,

--- 35 unchanged lines hidden ---