gcc-ipq806x.c (e95e825333eda345d812b461301dad50021d5487) gcc-ipq806x.c (cb02866f9a740fb9fb8ff19698a69290da4057e5)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>

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20#include "common.h"
21#include "clk-regmap.h"
22#include "clk-pll.h"
23#include "clk-rcg.h"
24#include "clk-branch.h"
25#include "clk-hfpll.h"
26#include "reset.h"
27
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>

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20#include "common.h"
21#include "clk-regmap.h"
22#include "clk-pll.h"
23#include "clk-rcg.h"
24#include "clk-branch.h"
25#include "clk-hfpll.h"
26#include "reset.h"
27
28static const struct clk_parent_data gcc_pxo[] = {
29 { .fw_name = "pxo", .name = "pxo" },
30};
31
28static struct clk_pll pll0 = {
29 .l_reg = 0x30c4,
30 .m_reg = 0x30c8,
31 .n_reg = 0x30cc,
32 .config_reg = 0x30d4,
33 .mode_reg = 0x30c0,
34 .status_reg = 0x30d8,
35 .status_bit = 16,
36 .clkr.hw.init = &(struct clk_init_data){
37 .name = "pll0",
32static struct clk_pll pll0 = {
33 .l_reg = 0x30c4,
34 .m_reg = 0x30c8,
35 .n_reg = 0x30cc,
36 .config_reg = 0x30d4,
37 .mode_reg = 0x30c0,
38 .status_reg = 0x30d8,
39 .status_bit = 16,
40 .clkr.hw.init = &(struct clk_init_data){
41 .name = "pll0",
38 .parent_names = (const char *[]){ "pxo" },
42 .parent_data = gcc_pxo,
39 .num_parents = 1,
40 .ops = &clk_pll_ops,
41 },
42};
43
44static struct clk_regmap pll0_vote = {
45 .enable_reg = 0x34c0,
46 .enable_mask = BIT(0),
47 .hw.init = &(struct clk_init_data){
48 .name = "pll0_vote",
43 .num_parents = 1,
44 .ops = &clk_pll_ops,
45 },
46};
47
48static struct clk_regmap pll0_vote = {
49 .enable_reg = 0x34c0,
50 .enable_mask = BIT(0),
51 .hw.init = &(struct clk_init_data){
52 .name = "pll0_vote",
49 .parent_names = (const char *[]){ "pll0" },
53 .parent_hws = (const struct clk_hw*[]){
54 &pll0.clkr.hw,
55 },
50 .num_parents = 1,
51 .ops = &clk_pll_vote_ops,
52 },
53};
54
55static struct clk_pll pll3 = {
56 .l_reg = 0x3164,
57 .m_reg = 0x3168,
58 .n_reg = 0x316c,
59 .config_reg = 0x3174,
60 .mode_reg = 0x3160,
61 .status_reg = 0x3178,
62 .status_bit = 16,
63 .clkr.hw.init = &(struct clk_init_data){
64 .name = "pll3",
56 .num_parents = 1,
57 .ops = &clk_pll_vote_ops,
58 },
59};
60
61static struct clk_pll pll3 = {
62 .l_reg = 0x3164,
63 .m_reg = 0x3168,
64 .n_reg = 0x316c,
65 .config_reg = 0x3174,
66 .mode_reg = 0x3160,
67 .status_reg = 0x3178,
68 .status_bit = 16,
69 .clkr.hw.init = &(struct clk_init_data){
70 .name = "pll3",
65 .parent_names = (const char *[]){ "pxo" },
71 .parent_data = gcc_pxo,
66 .num_parents = 1,
67 .ops = &clk_pll_ops,
68 },
69};
70
71static struct clk_regmap pll4_vote = {
72 .enable_reg = 0x34c0,
73 .enable_mask = BIT(4),

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84 .m_reg = 0x3148,
85 .n_reg = 0x314c,
86 .config_reg = 0x3154,
87 .mode_reg = 0x3140,
88 .status_reg = 0x3158,
89 .status_bit = 16,
90 .clkr.hw.init = &(struct clk_init_data){
91 .name = "pll8",
72 .num_parents = 1,
73 .ops = &clk_pll_ops,
74 },
75};
76
77static struct clk_regmap pll4_vote = {
78 .enable_reg = 0x34c0,
79 .enable_mask = BIT(4),

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90 .m_reg = 0x3148,
91 .n_reg = 0x314c,
92 .config_reg = 0x3154,
93 .mode_reg = 0x3140,
94 .status_reg = 0x3158,
95 .status_bit = 16,
96 .clkr.hw.init = &(struct clk_init_data){
97 .name = "pll8",
92 .parent_names = (const char *[]){ "pxo" },
98 .parent_data = gcc_pxo,
93 .num_parents = 1,
94 .ops = &clk_pll_ops,
95 },
96};
97
98static struct clk_regmap pll8_vote = {
99 .enable_reg = 0x34c0,
100 .enable_mask = BIT(8),
101 .hw.init = &(struct clk_init_data){
102 .name = "pll8_vote",
99 .num_parents = 1,
100 .ops = &clk_pll_ops,
101 },
102};
103
104static struct clk_regmap pll8_vote = {
105 .enable_reg = 0x34c0,
106 .enable_mask = BIT(8),
107 .hw.init = &(struct clk_init_data){
108 .name = "pll8_vote",
103 .parent_names = (const char *[]){ "pll8" },
109 .parent_hws = (const struct clk_hw*[]){
110 &pll8.clkr.hw,
111 },
104 .num_parents = 1,
105 .ops = &clk_pll_vote_ops,
106 },
107};
108
109static struct hfpll_data hfpll0_data = {
110 .mode_reg = 0x3200,
111 .l_reg = 0x3208,

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118 .droop_val = 0x0108c000,
119 .min_rate = 600000000UL,
120 .max_rate = 1800000000UL,
121};
122
123static struct clk_hfpll hfpll0 = {
124 .d = &hfpll0_data,
125 .clkr.hw.init = &(struct clk_init_data){
112 .num_parents = 1,
113 .ops = &clk_pll_vote_ops,
114 },
115};
116
117static struct hfpll_data hfpll0_data = {
118 .mode_reg = 0x3200,
119 .l_reg = 0x3208,

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126 .droop_val = 0x0108c000,
127 .min_rate = 600000000UL,
128 .max_rate = 1800000000UL,
129};
130
131static struct clk_hfpll hfpll0 = {
132 .d = &hfpll0_data,
133 .clkr.hw.init = &(struct clk_init_data){
126 .parent_names = (const char *[]){ "pxo" },
134 .parent_data = gcc_pxo,
127 .num_parents = 1,
128 .name = "hfpll0",
129 .ops = &clk_ops_hfpll,
130 .flags = CLK_IGNORE_UNUSED,
131 },
132 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
133};
134

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144 .droop_val = 0x0108c000,
145 .min_rate = 600000000UL,
146 .max_rate = 1800000000UL,
147};
148
149static struct clk_hfpll hfpll1 = {
150 .d = &hfpll1_data,
151 .clkr.hw.init = &(struct clk_init_data){
135 .num_parents = 1,
136 .name = "hfpll0",
137 .ops = &clk_ops_hfpll,
138 .flags = CLK_IGNORE_UNUSED,
139 },
140 .lock = __SPIN_LOCK_UNLOCKED(hfpll0.lock),
141};
142

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152 .droop_val = 0x0108c000,
153 .min_rate = 600000000UL,
154 .max_rate = 1800000000UL,
155};
156
157static struct clk_hfpll hfpll1 = {
158 .d = &hfpll1_data,
159 .clkr.hw.init = &(struct clk_init_data){
152 .parent_names = (const char *[]){ "pxo" },
160 .parent_data = gcc_pxo,
153 .num_parents = 1,
154 .name = "hfpll1",
155 .ops = &clk_ops_hfpll,
156 .flags = CLK_IGNORE_UNUSED,
157 },
158 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
159};
160

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170 .droop_val = 0x0108c000,
171 .min_rate = 600000000UL,
172 .max_rate = 1800000000UL,
173};
174
175static struct clk_hfpll hfpll_l2 = {
176 .d = &hfpll_l2_data,
177 .clkr.hw.init = &(struct clk_init_data){
161 .num_parents = 1,
162 .name = "hfpll1",
163 .ops = &clk_ops_hfpll,
164 .flags = CLK_IGNORE_UNUSED,
165 },
166 .lock = __SPIN_LOCK_UNLOCKED(hfpll1.lock),
167};
168

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178 .droop_val = 0x0108c000,
179 .min_rate = 600000000UL,
180 .max_rate = 1800000000UL,
181};
182
183static struct clk_hfpll hfpll_l2 = {
184 .d = &hfpll_l2_data,
185 .clkr.hw.init = &(struct clk_init_data){
178 .parent_names = (const char *[]){ "pxo" },
186 .parent_data = gcc_pxo,
179 .num_parents = 1,
180 .name = "hfpll_l2",
181 .ops = &clk_ops_hfpll,
182 .flags = CLK_IGNORE_UNUSED,
183 },
184 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
185};
186
187static struct clk_pll pll14 = {
188 .l_reg = 0x31c4,
189 .m_reg = 0x31c8,
190 .n_reg = 0x31cc,
191 .config_reg = 0x31d4,
192 .mode_reg = 0x31c0,
193 .status_reg = 0x31d8,
194 .status_bit = 16,
195 .clkr.hw.init = &(struct clk_init_data){
196 .name = "pll14",
187 .num_parents = 1,
188 .name = "hfpll_l2",
189 .ops = &clk_ops_hfpll,
190 .flags = CLK_IGNORE_UNUSED,
191 },
192 .lock = __SPIN_LOCK_UNLOCKED(hfpll_l2.lock),
193};
194
195static struct clk_pll pll14 = {
196 .l_reg = 0x31c4,
197 .m_reg = 0x31c8,
198 .n_reg = 0x31cc,
199 .config_reg = 0x31d4,
200 .mode_reg = 0x31c0,
201 .status_reg = 0x31d8,
202 .status_bit = 16,
203 .clkr.hw.init = &(struct clk_init_data){
204 .name = "pll14",
197 .parent_names = (const char *[]){ "pxo" },
205 .parent_data = gcc_pxo,
198 .num_parents = 1,
199 .ops = &clk_pll_ops,
200 },
201};
202
203static struct clk_regmap pll14_vote = {
204 .enable_reg = 0x34c0,
205 .enable_mask = BIT(14),
206 .hw.init = &(struct clk_init_data){
207 .name = "pll14_vote",
206 .num_parents = 1,
207 .ops = &clk_pll_ops,
208 },
209};
210
211static struct clk_regmap pll14_vote = {
212 .enable_reg = 0x34c0,
213 .enable_mask = BIT(14),
214 .hw.init = &(struct clk_init_data){
215 .name = "pll14_vote",
208 .parent_names = (const char *[]){ "pll14" },
216 .parent_hws = (const struct clk_hw*[]){
217 &pll14.clkr.hw,
218 },
209 .num_parents = 1,
210 .ops = &clk_pll_vote_ops,
211 },
212};
213
214#define NSS_PLL_RATE(f, _l, _m, _n, i) \
215 { \
216 .freq = f, \

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233 .mode_reg = 0x31a0,
234 .status_reg = 0x31b8,
235 .status_bit = 16,
236 .post_div_shift = 16,
237 .post_div_width = 1,
238 .freq_tbl = pll18_freq_tbl,
239 .clkr.hw.init = &(struct clk_init_data){
240 .name = "pll18",
219 .num_parents = 1,
220 .ops = &clk_pll_vote_ops,
221 },
222};
223
224#define NSS_PLL_RATE(f, _l, _m, _n, i) \
225 { \
226 .freq = f, \

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243 .mode_reg = 0x31a0,
244 .status_reg = 0x31b8,
245 .status_bit = 16,
246 .post_div_shift = 16,
247 .post_div_width = 1,
248 .freq_tbl = pll18_freq_tbl,
249 .clkr.hw.init = &(struct clk_init_data){
250 .name = "pll18",
241 .parent_names = (const char *[]){ "pxo" },
251 .parent_data = gcc_pxo,
242 .num_parents = 1,
243 .ops = &clk_pll_ops,
244 },
245};
246
247enum {
248 P_PXO,
249 P_PLL8,

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254 P_PLL18,
255};
256
257static const struct parent_map gcc_pxo_pll8_map[] = {
258 { P_PXO, 0 },
259 { P_PLL8, 3 }
260};
261
252 .num_parents = 1,
253 .ops = &clk_pll_ops,
254 },
255};
256
257enum {
258 P_PXO,
259 P_PLL8,

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264 P_PLL18,
265};
266
267static const struct parent_map gcc_pxo_pll8_map[] = {
268 { P_PXO, 0 },
269 { P_PLL8, 3 }
270};
271
262static const char * const gcc_pxo_pll8[] = {
263 "pxo",
264 "pll8_vote",
272static const struct clk_parent_data gcc_pxo_pll8[] = {
273 { .fw_name = "pxo", .name = "pxo" },
274 { .hw = &pll8_vote.hw },
265};
266
267static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
268 { P_PXO, 0 },
269 { P_PLL8, 3 },
270 { P_CXO, 5 }
271};
272
275};
276
277static const struct parent_map gcc_pxo_pll8_cxo_map[] = {
278 { P_PXO, 0 },
279 { P_PLL8, 3 },
280 { P_CXO, 5 }
281};
282
273static const char * const gcc_pxo_pll8_cxo[] = {
274 "pxo",
275 "pll8_vote",
276 "cxo",
283static const struct clk_parent_data gcc_pxo_pll8_cxo[] = {
284 { .fw_name = "pxo", .name = "pxo" },
285 { .hw = &pll8_vote.hw },
286 { .fw_name = "cxo", .name = "cxo" },
277};
278
279static const struct parent_map gcc_pxo_pll3_map[] = {
280 { P_PXO, 0 },
281 { P_PLL3, 1 }
282};
283
284static const struct parent_map gcc_pxo_pll3_sata_map[] = {
285 { P_PXO, 0 },
286 { P_PLL3, 6 }
287};
288
287};
288
289static const struct parent_map gcc_pxo_pll3_map[] = {
290 { P_PXO, 0 },
291 { P_PLL3, 1 }
292};
293
294static const struct parent_map gcc_pxo_pll3_sata_map[] = {
295 { P_PXO, 0 },
296 { P_PLL3, 6 }
297};
298
289static const char * const gcc_pxo_pll3[] = {
290 "pxo",
291 "pll3",
299static const struct clk_parent_data gcc_pxo_pll3[] = {
300 { .fw_name = "pxo", .name = "pxo" },
301 { .hw = &pll3.clkr.hw },
292};
293
294static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
295 { P_PXO, 0 },
296 { P_PLL8, 3 },
297 { P_PLL0, 2 }
298};
299
302};
303
304static const struct parent_map gcc_pxo_pll8_pll0_map[] = {
305 { P_PXO, 0 },
306 { P_PLL8, 3 },
307 { P_PLL0, 2 }
308};
309
300static const char * const gcc_pxo_pll8_pll0[] = {
301 "pxo",
302 "pll8_vote",
303 "pll0_vote",
310static const struct clk_parent_data gcc_pxo_pll8_pll0[] = {
311 { .fw_name = "pxo", .name = "pxo" },
312 { .hw = &pll8_vote.hw },
313 { .hw = &pll0_vote.hw },
304};
305
306static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
307 { P_PXO, 0 },
308 { P_PLL8, 4 },
309 { P_PLL0, 2 },
310 { P_PLL14, 5 },
311 { P_PLL18, 1 }
312};
313
314};
315
316static const struct parent_map gcc_pxo_pll8_pll14_pll18_pll0_map[] = {
317 { P_PXO, 0 },
318 { P_PLL8, 4 },
319 { P_PLL0, 2 },
320 { P_PLL14, 5 },
321 { P_PLL18, 1 }
322};
323
314static const char * const gcc_pxo_pll8_pll14_pll18_pll0[] = {
315 "pxo",
316 "pll8_vote",
317 "pll0_vote",
318 "pll14",
319 "pll18",
324static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
325 { .fw_name = "pxo", .name = "pxo" },
326 { .hw = &pll8_vote.hw },
327 { .hw = &pll0_vote.hw },
328 { .hw = &pll14.clkr.hw },
329 { .hw = &pll18.clkr.hw },
320};
321
322static struct freq_tbl clk_tbl_gsbi_uart[] = {
323 { 1843200, P_PLL8, 2, 6, 625 },
324 { 3686400, P_PLL8, 2, 12, 625 },
325 { 7372800, P_PLL8, 2, 24, 625 },
326 { 14745600, P_PLL8, 2, 48, 625 },
327 { 16000000, P_PLL8, 4, 1, 6 },

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357 .parent_map = gcc_pxo_pll8_map,
358 },
359 .freq_tbl = clk_tbl_gsbi_uart,
360 .clkr = {
361 .enable_reg = 0x29d4,
362 .enable_mask = BIT(11),
363 .hw.init = &(struct clk_init_data){
364 .name = "gsbi1_uart_src",
330};
331
332static struct freq_tbl clk_tbl_gsbi_uart[] = {
333 { 1843200, P_PLL8, 2, 6, 625 },
334 { 3686400, P_PLL8, 2, 12, 625 },
335 { 7372800, P_PLL8, 2, 24, 625 },
336 { 14745600, P_PLL8, 2, 48, 625 },
337 { 16000000, P_PLL8, 4, 1, 6 },

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367 .parent_map = gcc_pxo_pll8_map,
368 },
369 .freq_tbl = clk_tbl_gsbi_uart,
370 .clkr = {
371 .enable_reg = 0x29d4,
372 .enable_mask = BIT(11),
373 .hw.init = &(struct clk_init_data){
374 .name = "gsbi1_uart_src",
365 .parent_names = gcc_pxo_pll8,
375 .parent_data = gcc_pxo_pll8,
366 .num_parents = 2,
367 .ops = &clk_rcg_ops,
368 .flags = CLK_SET_PARENT_GATE,
369 },
370 },
371};
372
373static struct clk_branch gsbi1_uart_clk = {
374 .halt_reg = 0x2fcc,
375 .halt_bit = 12,
376 .clkr = {
377 .enable_reg = 0x29d4,
378 .enable_mask = BIT(9),
379 .hw.init = &(struct clk_init_data){
380 .name = "gsbi1_uart_clk",
376 .num_parents = 2,
377 .ops = &clk_rcg_ops,
378 .flags = CLK_SET_PARENT_GATE,
379 },
380 },
381};
382
383static struct clk_branch gsbi1_uart_clk = {
384 .halt_reg = 0x2fcc,
385 .halt_bit = 12,
386 .clkr = {
387 .enable_reg = 0x29d4,
388 .enable_mask = BIT(9),
389 .hw.init = &(struct clk_init_data){
390 .name = "gsbi1_uart_clk",
381 .parent_names = (const char *[]){
382 "gsbi1_uart_src",
391 .parent_hws = (const struct clk_hw*[]){
392 &gsbi1_uart_src.clkr.hw,
383 },
384 .num_parents = 1,
385 .ops = &clk_branch_ops,
386 .flags = CLK_SET_RATE_PARENT,
387 },
388 },
389};
390

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408 .parent_map = gcc_pxo_pll8_map,
409 },
410 .freq_tbl = clk_tbl_gsbi_uart,
411 .clkr = {
412 .enable_reg = 0x29f4,
413 .enable_mask = BIT(11),
414 .hw.init = &(struct clk_init_data){
415 .name = "gsbi2_uart_src",
393 },
394 .num_parents = 1,
395 .ops = &clk_branch_ops,
396 .flags = CLK_SET_RATE_PARENT,
397 },
398 },
399};
400

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418 .parent_map = gcc_pxo_pll8_map,
419 },
420 .freq_tbl = clk_tbl_gsbi_uart,
421 .clkr = {
422 .enable_reg = 0x29f4,
423 .enable_mask = BIT(11),
424 .hw.init = &(struct clk_init_data){
425 .name = "gsbi2_uart_src",
416 .parent_names = gcc_pxo_pll8,
426 .parent_data = gcc_pxo_pll8,
417 .num_parents = 2,
418 .ops = &clk_rcg_ops,
419 .flags = CLK_SET_PARENT_GATE,
420 },
421 },
422};
423
424static struct clk_branch gsbi2_uart_clk = {
425 .halt_reg = 0x2fcc,
426 .halt_bit = 8,
427 .clkr = {
428 .enable_reg = 0x29f4,
429 .enable_mask = BIT(9),
430 .hw.init = &(struct clk_init_data){
431 .name = "gsbi2_uart_clk",
427 .num_parents = 2,
428 .ops = &clk_rcg_ops,
429 .flags = CLK_SET_PARENT_GATE,
430 },
431 },
432};
433
434static struct clk_branch gsbi2_uart_clk = {
435 .halt_reg = 0x2fcc,
436 .halt_bit = 8,
437 .clkr = {
438 .enable_reg = 0x29f4,
439 .enable_mask = BIT(9),
440 .hw.init = &(struct clk_init_data){
441 .name = "gsbi2_uart_clk",
432 .parent_names = (const char *[]){
433 "gsbi2_uart_src",
442 .parent_hws = (const struct clk_hw*[]){
443 &gsbi2_uart_src.clkr.hw,
434 },
435 .num_parents = 1,
436 .ops = &clk_branch_ops,
437 .flags = CLK_SET_RATE_PARENT,
438 },
439 },
440};
441

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459 .parent_map = gcc_pxo_pll8_map,
460 },
461 .freq_tbl = clk_tbl_gsbi_uart,
462 .clkr = {
463 .enable_reg = 0x2a34,
464 .enable_mask = BIT(11),
465 .hw.init = &(struct clk_init_data){
466 .name = "gsbi4_uart_src",
444 },
445 .num_parents = 1,
446 .ops = &clk_branch_ops,
447 .flags = CLK_SET_RATE_PARENT,
448 },
449 },
450};
451

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469 .parent_map = gcc_pxo_pll8_map,
470 },
471 .freq_tbl = clk_tbl_gsbi_uart,
472 .clkr = {
473 .enable_reg = 0x2a34,
474 .enable_mask = BIT(11),
475 .hw.init = &(struct clk_init_data){
476 .name = "gsbi4_uart_src",
467 .parent_names = gcc_pxo_pll8,
477 .parent_data = gcc_pxo_pll8,
468 .num_parents = 2,
469 .ops = &clk_rcg_ops,
470 .flags = CLK_SET_PARENT_GATE,
471 },
472 },
473};
474
475static struct clk_branch gsbi4_uart_clk = {
476 .halt_reg = 0x2fd0,
477 .halt_bit = 26,
478 .clkr = {
479 .enable_reg = 0x2a34,
480 .enable_mask = BIT(9),
481 .hw.init = &(struct clk_init_data){
482 .name = "gsbi4_uart_clk",
478 .num_parents = 2,
479 .ops = &clk_rcg_ops,
480 .flags = CLK_SET_PARENT_GATE,
481 },
482 },
483};
484
485static struct clk_branch gsbi4_uart_clk = {
486 .halt_reg = 0x2fd0,
487 .halt_bit = 26,
488 .clkr = {
489 .enable_reg = 0x2a34,
490 .enable_mask = BIT(9),
491 .hw.init = &(struct clk_init_data){
492 .name = "gsbi4_uart_clk",
483 .parent_names = (const char *[]){
484 "gsbi4_uart_src",
493 .parent_hws = (const struct clk_hw*[]){
494 &gsbi4_uart_src.clkr.hw,
485 },
486 .num_parents = 1,
487 .ops = &clk_branch_ops,
488 .flags = CLK_SET_RATE_PARENT,
489 },
490 },
491};
492

--- 17 unchanged lines hidden (view full) ---

510 .parent_map = gcc_pxo_pll8_map,
511 },
512 .freq_tbl = clk_tbl_gsbi_uart,
513 .clkr = {
514 .enable_reg = 0x2a54,
515 .enable_mask = BIT(11),
516 .hw.init = &(struct clk_init_data){
517 .name = "gsbi5_uart_src",
495 },
496 .num_parents = 1,
497 .ops = &clk_branch_ops,
498 .flags = CLK_SET_RATE_PARENT,
499 },
500 },
501};
502

--- 17 unchanged lines hidden (view full) ---

520 .parent_map = gcc_pxo_pll8_map,
521 },
522 .freq_tbl = clk_tbl_gsbi_uart,
523 .clkr = {
524 .enable_reg = 0x2a54,
525 .enable_mask = BIT(11),
526 .hw.init = &(struct clk_init_data){
527 .name = "gsbi5_uart_src",
518 .parent_names = gcc_pxo_pll8,
528 .parent_data = gcc_pxo_pll8,
519 .num_parents = 2,
520 .ops = &clk_rcg_ops,
521 .flags = CLK_SET_PARENT_GATE,
522 },
523 },
524};
525
526static struct clk_branch gsbi5_uart_clk = {
527 .halt_reg = 0x2fd0,
528 .halt_bit = 22,
529 .clkr = {
530 .enable_reg = 0x2a54,
531 .enable_mask = BIT(9),
532 .hw.init = &(struct clk_init_data){
533 .name = "gsbi5_uart_clk",
529 .num_parents = 2,
530 .ops = &clk_rcg_ops,
531 .flags = CLK_SET_PARENT_GATE,
532 },
533 },
534};
535
536static struct clk_branch gsbi5_uart_clk = {
537 .halt_reg = 0x2fd0,
538 .halt_bit = 22,
539 .clkr = {
540 .enable_reg = 0x2a54,
541 .enable_mask = BIT(9),
542 .hw.init = &(struct clk_init_data){
543 .name = "gsbi5_uart_clk",
534 .parent_names = (const char *[]){
535 "gsbi5_uart_src",
544 .parent_hws = (const struct clk_hw*[]){
545 &gsbi5_uart_src.clkr.hw,
536 },
537 .num_parents = 1,
538 .ops = &clk_branch_ops,
539 .flags = CLK_SET_RATE_PARENT,
540 },
541 },
542};
543

--- 17 unchanged lines hidden (view full) ---

561 .parent_map = gcc_pxo_pll8_map,
562 },
563 .freq_tbl = clk_tbl_gsbi_uart,
564 .clkr = {
565 .enable_reg = 0x2a74,
566 .enable_mask = BIT(11),
567 .hw.init = &(struct clk_init_data){
568 .name = "gsbi6_uart_src",
546 },
547 .num_parents = 1,
548 .ops = &clk_branch_ops,
549 .flags = CLK_SET_RATE_PARENT,
550 },
551 },
552};
553

--- 17 unchanged lines hidden (view full) ---

571 .parent_map = gcc_pxo_pll8_map,
572 },
573 .freq_tbl = clk_tbl_gsbi_uart,
574 .clkr = {
575 .enable_reg = 0x2a74,
576 .enable_mask = BIT(11),
577 .hw.init = &(struct clk_init_data){
578 .name = "gsbi6_uart_src",
569 .parent_names = gcc_pxo_pll8,
579 .parent_data = gcc_pxo_pll8,
570 .num_parents = 2,
571 .ops = &clk_rcg_ops,
572 .flags = CLK_SET_PARENT_GATE,
573 },
574 },
575};
576
577static struct clk_branch gsbi6_uart_clk = {
578 .halt_reg = 0x2fd0,
579 .halt_bit = 18,
580 .clkr = {
581 .enable_reg = 0x2a74,
582 .enable_mask = BIT(9),
583 .hw.init = &(struct clk_init_data){
584 .name = "gsbi6_uart_clk",
580 .num_parents = 2,
581 .ops = &clk_rcg_ops,
582 .flags = CLK_SET_PARENT_GATE,
583 },
584 },
585};
586
587static struct clk_branch gsbi6_uart_clk = {
588 .halt_reg = 0x2fd0,
589 .halt_bit = 18,
590 .clkr = {
591 .enable_reg = 0x2a74,
592 .enable_mask = BIT(9),
593 .hw.init = &(struct clk_init_data){
594 .name = "gsbi6_uart_clk",
585 .parent_names = (const char *[]){
586 "gsbi6_uart_src",
595 .parent_hws = (const struct clk_hw*[]){
596 &gsbi6_uart_src.clkr.hw,
587 },
588 .num_parents = 1,
589 .ops = &clk_branch_ops,
590 .flags = CLK_SET_RATE_PARENT,
591 },
592 },
593};
594

--- 17 unchanged lines hidden (view full) ---

612 .parent_map = gcc_pxo_pll8_map,
613 },
614 .freq_tbl = clk_tbl_gsbi_uart,
615 .clkr = {
616 .enable_reg = 0x2a94,
617 .enable_mask = BIT(11),
618 .hw.init = &(struct clk_init_data){
619 .name = "gsbi7_uart_src",
597 },
598 .num_parents = 1,
599 .ops = &clk_branch_ops,
600 .flags = CLK_SET_RATE_PARENT,
601 },
602 },
603};
604

--- 17 unchanged lines hidden (view full) ---

622 .parent_map = gcc_pxo_pll8_map,
623 },
624 .freq_tbl = clk_tbl_gsbi_uart,
625 .clkr = {
626 .enable_reg = 0x2a94,
627 .enable_mask = BIT(11),
628 .hw.init = &(struct clk_init_data){
629 .name = "gsbi7_uart_src",
620 .parent_names = gcc_pxo_pll8,
630 .parent_data = gcc_pxo_pll8,
621 .num_parents = 2,
622 .ops = &clk_rcg_ops,
623 .flags = CLK_SET_PARENT_GATE,
624 },
625 },
626};
627
628static struct clk_branch gsbi7_uart_clk = {
629 .halt_reg = 0x2fd0,
630 .halt_bit = 14,
631 .clkr = {
632 .enable_reg = 0x2a94,
633 .enable_mask = BIT(9),
634 .hw.init = &(struct clk_init_data){
635 .name = "gsbi7_uart_clk",
631 .num_parents = 2,
632 .ops = &clk_rcg_ops,
633 .flags = CLK_SET_PARENT_GATE,
634 },
635 },
636};
637
638static struct clk_branch gsbi7_uart_clk = {
639 .halt_reg = 0x2fd0,
640 .halt_bit = 14,
641 .clkr = {
642 .enable_reg = 0x2a94,
643 .enable_mask = BIT(9),
644 .hw.init = &(struct clk_init_data){
645 .name = "gsbi7_uart_clk",
636 .parent_names = (const char *[]){
637 "gsbi7_uart_src",
646 .parent_hws = (const struct clk_hw*[]){
647 &gsbi7_uart_src.clkr.hw,
638 },
639 .num_parents = 1,
640 .ops = &clk_branch_ops,
641 .flags = CLK_SET_RATE_PARENT,
642 },
643 },
644};
645

--- 30 unchanged lines hidden (view full) ---

676 .parent_map = gcc_pxo_pll8_map,
677 },
678 .freq_tbl = clk_tbl_gsbi_qup,
679 .clkr = {
680 .enable_reg = 0x29cc,
681 .enable_mask = BIT(11),
682 .hw.init = &(struct clk_init_data){
683 .name = "gsbi1_qup_src",
648 },
649 .num_parents = 1,
650 .ops = &clk_branch_ops,
651 .flags = CLK_SET_RATE_PARENT,
652 },
653 },
654};
655

--- 30 unchanged lines hidden (view full) ---

686 .parent_map = gcc_pxo_pll8_map,
687 },
688 .freq_tbl = clk_tbl_gsbi_qup,
689 .clkr = {
690 .enable_reg = 0x29cc,
691 .enable_mask = BIT(11),
692 .hw.init = &(struct clk_init_data){
693 .name = "gsbi1_qup_src",
684 .parent_names = gcc_pxo_pll8,
694 .parent_data = gcc_pxo_pll8,
685 .num_parents = 2,
686 .ops = &clk_rcg_ops,
687 .flags = CLK_SET_PARENT_GATE,
688 },
689 },
690};
691
692static struct clk_branch gsbi1_qup_clk = {
693 .halt_reg = 0x2fcc,
694 .halt_bit = 11,
695 .clkr = {
696 .enable_reg = 0x29cc,
697 .enable_mask = BIT(9),
698 .hw.init = &(struct clk_init_data){
699 .name = "gsbi1_qup_clk",
695 .num_parents = 2,
696 .ops = &clk_rcg_ops,
697 .flags = CLK_SET_PARENT_GATE,
698 },
699 },
700};
701
702static struct clk_branch gsbi1_qup_clk = {
703 .halt_reg = 0x2fcc,
704 .halt_bit = 11,
705 .clkr = {
706 .enable_reg = 0x29cc,
707 .enable_mask = BIT(9),
708 .hw.init = &(struct clk_init_data){
709 .name = "gsbi1_qup_clk",
700 .parent_names = (const char *[]){ "gsbi1_qup_src" },
710 .parent_hws = (const struct clk_hw*[]){
711 &gsbi1_qup_src.clkr.hw,
712 },
701 .num_parents = 1,
702 .ops = &clk_branch_ops,
703 .flags = CLK_SET_RATE_PARENT,
704 },
705 },
706};
707
708static struct clk_rcg gsbi2_qup_src = {

--- 16 unchanged lines hidden (view full) ---

725 .parent_map = gcc_pxo_pll8_map,
726 },
727 .freq_tbl = clk_tbl_gsbi_qup,
728 .clkr = {
729 .enable_reg = 0x29ec,
730 .enable_mask = BIT(11),
731 .hw.init = &(struct clk_init_data){
732 .name = "gsbi2_qup_src",
713 .num_parents = 1,
714 .ops = &clk_branch_ops,
715 .flags = CLK_SET_RATE_PARENT,
716 },
717 },
718};
719
720static struct clk_rcg gsbi2_qup_src = {

--- 16 unchanged lines hidden (view full) ---

737 .parent_map = gcc_pxo_pll8_map,
738 },
739 .freq_tbl = clk_tbl_gsbi_qup,
740 .clkr = {
741 .enable_reg = 0x29ec,
742 .enable_mask = BIT(11),
743 .hw.init = &(struct clk_init_data){
744 .name = "gsbi2_qup_src",
733 .parent_names = gcc_pxo_pll8,
745 .parent_data = gcc_pxo_pll8,
734 .num_parents = 2,
735 .ops = &clk_rcg_ops,
736 .flags = CLK_SET_PARENT_GATE,
737 },
738 },
739};
740
741static struct clk_branch gsbi2_qup_clk = {
742 .halt_reg = 0x2fcc,
743 .halt_bit = 6,
744 .clkr = {
745 .enable_reg = 0x29ec,
746 .enable_mask = BIT(9),
747 .hw.init = &(struct clk_init_data){
748 .name = "gsbi2_qup_clk",
746 .num_parents = 2,
747 .ops = &clk_rcg_ops,
748 .flags = CLK_SET_PARENT_GATE,
749 },
750 },
751};
752
753static struct clk_branch gsbi2_qup_clk = {
754 .halt_reg = 0x2fcc,
755 .halt_bit = 6,
756 .clkr = {
757 .enable_reg = 0x29ec,
758 .enable_mask = BIT(9),
759 .hw.init = &(struct clk_init_data){
760 .name = "gsbi2_qup_clk",
749 .parent_names = (const char *[]){ "gsbi2_qup_src" },
761 .parent_hws = (const struct clk_hw*[]){
762 &gsbi2_qup_src.clkr.hw,
763 },
750 .num_parents = 1,
751 .ops = &clk_branch_ops,
752 .flags = CLK_SET_RATE_PARENT,
753 },
754 },
755};
756
757static struct clk_rcg gsbi4_qup_src = {

--- 16 unchanged lines hidden (view full) ---

774 .parent_map = gcc_pxo_pll8_map,
775 },
776 .freq_tbl = clk_tbl_gsbi_qup,
777 .clkr = {
778 .enable_reg = 0x2a2c,
779 .enable_mask = BIT(11),
780 .hw.init = &(struct clk_init_data){
781 .name = "gsbi4_qup_src",
764 .num_parents = 1,
765 .ops = &clk_branch_ops,
766 .flags = CLK_SET_RATE_PARENT,
767 },
768 },
769};
770
771static struct clk_rcg gsbi4_qup_src = {

--- 16 unchanged lines hidden (view full) ---

788 .parent_map = gcc_pxo_pll8_map,
789 },
790 .freq_tbl = clk_tbl_gsbi_qup,
791 .clkr = {
792 .enable_reg = 0x2a2c,
793 .enable_mask = BIT(11),
794 .hw.init = &(struct clk_init_data){
795 .name = "gsbi4_qup_src",
782 .parent_names = gcc_pxo_pll8,
796 .parent_data = gcc_pxo_pll8,
783 .num_parents = 2,
784 .ops = &clk_rcg_ops,
785 .flags = CLK_SET_PARENT_GATE,
786 },
787 },
788};
789
790static struct clk_branch gsbi4_qup_clk = {
791 .halt_reg = 0x2fd0,
792 .halt_bit = 24,
793 .clkr = {
794 .enable_reg = 0x2a2c,
795 .enable_mask = BIT(9),
796 .hw.init = &(struct clk_init_data){
797 .name = "gsbi4_qup_clk",
797 .num_parents = 2,
798 .ops = &clk_rcg_ops,
799 .flags = CLK_SET_PARENT_GATE,
800 },
801 },
802};
803
804static struct clk_branch gsbi4_qup_clk = {
805 .halt_reg = 0x2fd0,
806 .halt_bit = 24,
807 .clkr = {
808 .enable_reg = 0x2a2c,
809 .enable_mask = BIT(9),
810 .hw.init = &(struct clk_init_data){
811 .name = "gsbi4_qup_clk",
798 .parent_names = (const char *[]){ "gsbi4_qup_src" },
812 .parent_hws = (const struct clk_hw*[]){
813 &gsbi4_qup_src.clkr.hw,
814 },
799 .num_parents = 1,
800 .ops = &clk_branch_ops,
801 .flags = CLK_SET_RATE_PARENT,
802 },
803 },
804};
805
806static struct clk_rcg gsbi5_qup_src = {

--- 16 unchanged lines hidden (view full) ---

823 .parent_map = gcc_pxo_pll8_map,
824 },
825 .freq_tbl = clk_tbl_gsbi_qup,
826 .clkr = {
827 .enable_reg = 0x2a4c,
828 .enable_mask = BIT(11),
829 .hw.init = &(struct clk_init_data){
830 .name = "gsbi5_qup_src",
815 .num_parents = 1,
816 .ops = &clk_branch_ops,
817 .flags = CLK_SET_RATE_PARENT,
818 },
819 },
820};
821
822static struct clk_rcg gsbi5_qup_src = {

--- 16 unchanged lines hidden (view full) ---

839 .parent_map = gcc_pxo_pll8_map,
840 },
841 .freq_tbl = clk_tbl_gsbi_qup,
842 .clkr = {
843 .enable_reg = 0x2a4c,
844 .enable_mask = BIT(11),
845 .hw.init = &(struct clk_init_data){
846 .name = "gsbi5_qup_src",
831 .parent_names = gcc_pxo_pll8,
847 .parent_data = gcc_pxo_pll8,
832 .num_parents = 2,
833 .ops = &clk_rcg_ops,
834 .flags = CLK_SET_PARENT_GATE,
835 },
836 },
837};
838
839static struct clk_branch gsbi5_qup_clk = {
840 .halt_reg = 0x2fd0,
841 .halt_bit = 20,
842 .clkr = {
843 .enable_reg = 0x2a4c,
844 .enable_mask = BIT(9),
845 .hw.init = &(struct clk_init_data){
846 .name = "gsbi5_qup_clk",
848 .num_parents = 2,
849 .ops = &clk_rcg_ops,
850 .flags = CLK_SET_PARENT_GATE,
851 },
852 },
853};
854
855static struct clk_branch gsbi5_qup_clk = {
856 .halt_reg = 0x2fd0,
857 .halt_bit = 20,
858 .clkr = {
859 .enable_reg = 0x2a4c,
860 .enable_mask = BIT(9),
861 .hw.init = &(struct clk_init_data){
862 .name = "gsbi5_qup_clk",
847 .parent_names = (const char *[]){ "gsbi5_qup_src" },
863 .parent_hws = (const struct clk_hw*[]){
864 &gsbi5_qup_src.clkr.hw,
865 },
848 .num_parents = 1,
849 .ops = &clk_branch_ops,
850 .flags = CLK_SET_RATE_PARENT,
851 },
852 },
853};
854
855static struct clk_rcg gsbi6_qup_src = {

--- 16 unchanged lines hidden (view full) ---

872 .parent_map = gcc_pxo_pll8_map,
873 },
874 .freq_tbl = clk_tbl_gsbi_qup,
875 .clkr = {
876 .enable_reg = 0x2a6c,
877 .enable_mask = BIT(11),
878 .hw.init = &(struct clk_init_data){
879 .name = "gsbi6_qup_src",
866 .num_parents = 1,
867 .ops = &clk_branch_ops,
868 .flags = CLK_SET_RATE_PARENT,
869 },
870 },
871};
872
873static struct clk_rcg gsbi6_qup_src = {

--- 16 unchanged lines hidden (view full) ---

890 .parent_map = gcc_pxo_pll8_map,
891 },
892 .freq_tbl = clk_tbl_gsbi_qup,
893 .clkr = {
894 .enable_reg = 0x2a6c,
895 .enable_mask = BIT(11),
896 .hw.init = &(struct clk_init_data){
897 .name = "gsbi6_qup_src",
880 .parent_names = gcc_pxo_pll8,
898 .parent_data = gcc_pxo_pll8,
881 .num_parents = 2,
882 .ops = &clk_rcg_ops,
883 .flags = CLK_SET_PARENT_GATE,
884 },
885 },
886};
887
888static struct clk_branch gsbi6_qup_clk = {
889 .halt_reg = 0x2fd0,
890 .halt_bit = 16,
891 .clkr = {
892 .enable_reg = 0x2a6c,
893 .enable_mask = BIT(9),
894 .hw.init = &(struct clk_init_data){
895 .name = "gsbi6_qup_clk",
899 .num_parents = 2,
900 .ops = &clk_rcg_ops,
901 .flags = CLK_SET_PARENT_GATE,
902 },
903 },
904};
905
906static struct clk_branch gsbi6_qup_clk = {
907 .halt_reg = 0x2fd0,
908 .halt_bit = 16,
909 .clkr = {
910 .enable_reg = 0x2a6c,
911 .enable_mask = BIT(9),
912 .hw.init = &(struct clk_init_data){
913 .name = "gsbi6_qup_clk",
896 .parent_names = (const char *[]){ "gsbi6_qup_src" },
914 .parent_hws = (const struct clk_hw*[]){
915 &gsbi6_qup_src.clkr.hw,
916 },
897 .num_parents = 1,
898 .ops = &clk_branch_ops,
899 .flags = CLK_SET_RATE_PARENT,
900 },
901 },
902};
903
904static struct clk_rcg gsbi7_qup_src = {

--- 16 unchanged lines hidden (view full) ---

921 .parent_map = gcc_pxo_pll8_map,
922 },
923 .freq_tbl = clk_tbl_gsbi_qup,
924 .clkr = {
925 .enable_reg = 0x2a8c,
926 .enable_mask = BIT(11),
927 .hw.init = &(struct clk_init_data){
928 .name = "gsbi7_qup_src",
917 .num_parents = 1,
918 .ops = &clk_branch_ops,
919 .flags = CLK_SET_RATE_PARENT,
920 },
921 },
922};
923
924static struct clk_rcg gsbi7_qup_src = {

--- 16 unchanged lines hidden (view full) ---

941 .parent_map = gcc_pxo_pll8_map,
942 },
943 .freq_tbl = clk_tbl_gsbi_qup,
944 .clkr = {
945 .enable_reg = 0x2a8c,
946 .enable_mask = BIT(11),
947 .hw.init = &(struct clk_init_data){
948 .name = "gsbi7_qup_src",
929 .parent_names = gcc_pxo_pll8,
949 .parent_data = gcc_pxo_pll8,
930 .num_parents = 2,
931 .ops = &clk_rcg_ops,
932 .flags = CLK_SET_PARENT_GATE,
933 },
934 },
935};
936
937static struct clk_branch gsbi7_qup_clk = {
938 .halt_reg = 0x2fd0,
939 .halt_bit = 12,
940 .clkr = {
941 .enable_reg = 0x2a8c,
942 .enable_mask = BIT(9),
943 .hw.init = &(struct clk_init_data){
944 .name = "gsbi7_qup_clk",
950 .num_parents = 2,
951 .ops = &clk_rcg_ops,
952 .flags = CLK_SET_PARENT_GATE,
953 },
954 },
955};
956
957static struct clk_branch gsbi7_qup_clk = {
958 .halt_reg = 0x2fd0,
959 .halt_bit = 12,
960 .clkr = {
961 .enable_reg = 0x2a8c,
962 .enable_mask = BIT(9),
963 .hw.init = &(struct clk_init_data){
964 .name = "gsbi7_qup_clk",
945 .parent_names = (const char *[]){ "gsbi7_qup_src" },
965 .parent_hws = (const struct clk_hw*[]){
966 &gsbi7_qup_src.clkr.hw,
967 },
946 .num_parents = 1,
947 .ops = &clk_branch_ops,
948 .flags = CLK_SET_RATE_PARENT,
949 },
950 },
951};
952
953static struct clk_branch gsbi1_h_clk = {

--- 117 unchanged lines hidden (view full) ---

1071 .parent_map = gcc_pxo_pll8_cxo_map,
1072 },
1073 .freq_tbl = clk_tbl_gp,
1074 .clkr = {
1075 .enable_reg = 0x2d24,
1076 .enable_mask = BIT(11),
1077 .hw.init = &(struct clk_init_data){
1078 .name = "gp0_src",
968 .num_parents = 1,
969 .ops = &clk_branch_ops,
970 .flags = CLK_SET_RATE_PARENT,
971 },
972 },
973};
974
975static struct clk_branch gsbi1_h_clk = {

--- 117 unchanged lines hidden (view full) ---

1093 .parent_map = gcc_pxo_pll8_cxo_map,
1094 },
1095 .freq_tbl = clk_tbl_gp,
1096 .clkr = {
1097 .enable_reg = 0x2d24,
1098 .enable_mask = BIT(11),
1099 .hw.init = &(struct clk_init_data){
1100 .name = "gp0_src",
1079 .parent_names = gcc_pxo_pll8_cxo,
1101 .parent_data = gcc_pxo_pll8_cxo,
1080 .num_parents = 3,
1081 .ops = &clk_rcg_ops,
1082 .flags = CLK_SET_PARENT_GATE,
1083 },
1084 }
1085};
1086
1087static struct clk_branch gp0_clk = {
1088 .halt_reg = 0x2fd8,
1089 .halt_bit = 7,
1090 .clkr = {
1091 .enable_reg = 0x2d24,
1092 .enable_mask = BIT(9),
1093 .hw.init = &(struct clk_init_data){
1094 .name = "gp0_clk",
1102 .num_parents = 3,
1103 .ops = &clk_rcg_ops,
1104 .flags = CLK_SET_PARENT_GATE,
1105 },
1106 }
1107};
1108
1109static struct clk_branch gp0_clk = {
1110 .halt_reg = 0x2fd8,
1111 .halt_bit = 7,
1112 .clkr = {
1113 .enable_reg = 0x2d24,
1114 .enable_mask = BIT(9),
1115 .hw.init = &(struct clk_init_data){
1116 .name = "gp0_clk",
1095 .parent_names = (const char *[]){ "gp0_src" },
1117 .parent_hws = (const struct clk_hw*[]){
1118 &gp0_src.clkr.hw,
1119 },
1096 .num_parents = 1,
1097 .ops = &clk_branch_ops,
1098 .flags = CLK_SET_RATE_PARENT,
1099 },
1100 },
1101};
1102
1103static struct clk_rcg gp1_src = {

--- 16 unchanged lines hidden (view full) ---

1120 .parent_map = gcc_pxo_pll8_cxo_map,
1121 },
1122 .freq_tbl = clk_tbl_gp,
1123 .clkr = {
1124 .enable_reg = 0x2d44,
1125 .enable_mask = BIT(11),
1126 .hw.init = &(struct clk_init_data){
1127 .name = "gp1_src",
1120 .num_parents = 1,
1121 .ops = &clk_branch_ops,
1122 .flags = CLK_SET_RATE_PARENT,
1123 },
1124 },
1125};
1126
1127static struct clk_rcg gp1_src = {

--- 16 unchanged lines hidden (view full) ---

1144 .parent_map = gcc_pxo_pll8_cxo_map,
1145 },
1146 .freq_tbl = clk_tbl_gp,
1147 .clkr = {
1148 .enable_reg = 0x2d44,
1149 .enable_mask = BIT(11),
1150 .hw.init = &(struct clk_init_data){
1151 .name = "gp1_src",
1128 .parent_names = gcc_pxo_pll8_cxo,
1152 .parent_data = gcc_pxo_pll8_cxo,
1129 .num_parents = 3,
1130 .ops = &clk_rcg_ops,
1131 .flags = CLK_SET_RATE_GATE,
1132 },
1133 }
1134};
1135
1136static struct clk_branch gp1_clk = {
1137 .halt_reg = 0x2fd8,
1138 .halt_bit = 6,
1139 .clkr = {
1140 .enable_reg = 0x2d44,
1141 .enable_mask = BIT(9),
1142 .hw.init = &(struct clk_init_data){
1143 .name = "gp1_clk",
1153 .num_parents = 3,
1154 .ops = &clk_rcg_ops,
1155 .flags = CLK_SET_RATE_GATE,
1156 },
1157 }
1158};
1159
1160static struct clk_branch gp1_clk = {
1161 .halt_reg = 0x2fd8,
1162 .halt_bit = 6,
1163 .clkr = {
1164 .enable_reg = 0x2d44,
1165 .enable_mask = BIT(9),
1166 .hw.init = &(struct clk_init_data){
1167 .name = "gp1_clk",
1144 .parent_names = (const char *[]){ "gp1_src" },
1168 .parent_hws = (const struct clk_hw*[]){
1169 &gp1_src.clkr.hw,
1170 },
1145 .num_parents = 1,
1146 .ops = &clk_branch_ops,
1147 .flags = CLK_SET_RATE_PARENT,
1148 },
1149 },
1150};
1151
1152static struct clk_rcg gp2_src = {

--- 16 unchanged lines hidden (view full) ---

1169 .parent_map = gcc_pxo_pll8_cxo_map,
1170 },
1171 .freq_tbl = clk_tbl_gp,
1172 .clkr = {
1173 .enable_reg = 0x2d64,
1174 .enable_mask = BIT(11),
1175 .hw.init = &(struct clk_init_data){
1176 .name = "gp2_src",
1171 .num_parents = 1,
1172 .ops = &clk_branch_ops,
1173 .flags = CLK_SET_RATE_PARENT,
1174 },
1175 },
1176};
1177
1178static struct clk_rcg gp2_src = {

--- 16 unchanged lines hidden (view full) ---

1195 .parent_map = gcc_pxo_pll8_cxo_map,
1196 },
1197 .freq_tbl = clk_tbl_gp,
1198 .clkr = {
1199 .enable_reg = 0x2d64,
1200 .enable_mask = BIT(11),
1201 .hw.init = &(struct clk_init_data){
1202 .name = "gp2_src",
1177 .parent_names = gcc_pxo_pll8_cxo,
1203 .parent_data = gcc_pxo_pll8_cxo,
1178 .num_parents = 3,
1179 .ops = &clk_rcg_ops,
1180 .flags = CLK_SET_RATE_GATE,
1181 },
1182 }
1183};
1184
1185static struct clk_branch gp2_clk = {
1186 .halt_reg = 0x2fd8,
1187 .halt_bit = 5,
1188 .clkr = {
1189 .enable_reg = 0x2d64,
1190 .enable_mask = BIT(9),
1191 .hw.init = &(struct clk_init_data){
1192 .name = "gp2_clk",
1204 .num_parents = 3,
1205 .ops = &clk_rcg_ops,
1206 .flags = CLK_SET_RATE_GATE,
1207 },
1208 }
1209};
1210
1211static struct clk_branch gp2_clk = {
1212 .halt_reg = 0x2fd8,
1213 .halt_bit = 5,
1214 .clkr = {
1215 .enable_reg = 0x2d64,
1216 .enable_mask = BIT(9),
1217 .hw.init = &(struct clk_init_data){
1218 .name = "gp2_clk",
1193 .parent_names = (const char *[]){ "gp2_src" },
1219 .parent_hws = (const struct clk_hw*[]){
1220 &gp2_src.clkr.hw,
1221 },
1194 .num_parents = 1,
1195 .ops = &clk_branch_ops,
1196 .flags = CLK_SET_RATE_PARENT,
1197 },
1198 },
1199};
1200
1201static struct clk_branch pmem_clk = {

--- 21 unchanged lines hidden (view full) ---

1223 .src_sel_shift = 0,
1224 .parent_map = gcc_pxo_pll8_map,
1225 },
1226 .clkr = {
1227 .enable_reg = 0x2e80,
1228 .enable_mask = BIT(11),
1229 .hw.init = &(struct clk_init_data){
1230 .name = "prng_src",
1222 .num_parents = 1,
1223 .ops = &clk_branch_ops,
1224 .flags = CLK_SET_RATE_PARENT,
1225 },
1226 },
1227};
1228
1229static struct clk_branch pmem_clk = {

--- 21 unchanged lines hidden (view full) ---

1251 .src_sel_shift = 0,
1252 .parent_map = gcc_pxo_pll8_map,
1253 },
1254 .clkr = {
1255 .enable_reg = 0x2e80,
1256 .enable_mask = BIT(11),
1257 .hw.init = &(struct clk_init_data){
1258 .name = "prng_src",
1231 .parent_names = gcc_pxo_pll8,
1259 .parent_data = gcc_pxo_pll8,
1232 .num_parents = 2,
1233 .ops = &clk_rcg_ops,
1234 },
1235 },
1236};
1237
1238static struct clk_branch prng_clk = {
1239 .halt_reg = 0x2fd8,
1240 .halt_check = BRANCH_HALT_VOTED,
1241 .halt_bit = 10,
1242 .clkr = {
1243 .enable_reg = 0x3080,
1244 .enable_mask = BIT(10),
1245 .hw.init = &(struct clk_init_data){
1246 .name = "prng_clk",
1260 .num_parents = 2,
1261 .ops = &clk_rcg_ops,
1262 },
1263 },
1264};
1265
1266static struct clk_branch prng_clk = {
1267 .halt_reg = 0x2fd8,
1268 .halt_check = BRANCH_HALT_VOTED,
1269 .halt_bit = 10,
1270 .clkr = {
1271 .enable_reg = 0x3080,
1272 .enable_mask = BIT(10),
1273 .hw.init = &(struct clk_init_data){
1274 .name = "prng_clk",
1247 .parent_names = (const char *[]){ "prng_src" },
1275 .parent_hws = (const struct clk_hw*[]){
1276 &prng_src.clkr.hw,
1277 },
1248 .num_parents = 1,
1249 .ops = &clk_branch_ops,
1250 },
1251 },
1252};
1253
1254static const struct freq_tbl clk_tbl_sdc[] = {
1255 { 200000, P_PXO, 2, 2, 125 },

--- 29 unchanged lines hidden (view full) ---

1285 .parent_map = gcc_pxo_pll8_map,
1286 },
1287 .freq_tbl = clk_tbl_sdc,
1288 .clkr = {
1289 .enable_reg = 0x282c,
1290 .enable_mask = BIT(11),
1291 .hw.init = &(struct clk_init_data){
1292 .name = "sdc1_src",
1278 .num_parents = 1,
1279 .ops = &clk_branch_ops,
1280 },
1281 },
1282};
1283
1284static const struct freq_tbl clk_tbl_sdc[] = {
1285 { 200000, P_PXO, 2, 2, 125 },

--- 29 unchanged lines hidden (view full) ---

1315 .parent_map = gcc_pxo_pll8_map,
1316 },
1317 .freq_tbl = clk_tbl_sdc,
1318 .clkr = {
1319 .enable_reg = 0x282c,
1320 .enable_mask = BIT(11),
1321 .hw.init = &(struct clk_init_data){
1322 .name = "sdc1_src",
1293 .parent_names = gcc_pxo_pll8,
1323 .parent_data = gcc_pxo_pll8,
1294 .num_parents = 2,
1295 .ops = &clk_rcg_ops,
1296 },
1297 }
1298};
1299
1300static struct clk_branch sdc1_clk = {
1301 .halt_reg = 0x2fc8,
1302 .halt_bit = 6,
1303 .clkr = {
1304 .enable_reg = 0x282c,
1305 .enable_mask = BIT(9),
1306 .hw.init = &(struct clk_init_data){
1307 .name = "sdc1_clk",
1324 .num_parents = 2,
1325 .ops = &clk_rcg_ops,
1326 },
1327 }
1328};
1329
1330static struct clk_branch sdc1_clk = {
1331 .halt_reg = 0x2fc8,
1332 .halt_bit = 6,
1333 .clkr = {
1334 .enable_reg = 0x282c,
1335 .enable_mask = BIT(9),
1336 .hw.init = &(struct clk_init_data){
1337 .name = "sdc1_clk",
1308 .parent_names = (const char *[]){ "sdc1_src" },
1338 .parent_hws = (const struct clk_hw*[]){
1339 &sdc1_src.clkr.hw,
1340 },
1309 .num_parents = 1,
1310 .ops = &clk_branch_ops,
1311 .flags = CLK_SET_RATE_PARENT,
1312 },
1313 },
1314};
1315
1316static struct clk_rcg sdc3_src = {

--- 16 unchanged lines hidden (view full) ---

1333 .parent_map = gcc_pxo_pll8_map,
1334 },
1335 .freq_tbl = clk_tbl_sdc,
1336 .clkr = {
1337 .enable_reg = 0x286c,
1338 .enable_mask = BIT(11),
1339 .hw.init = &(struct clk_init_data){
1340 .name = "sdc3_src",
1341 .num_parents = 1,
1342 .ops = &clk_branch_ops,
1343 .flags = CLK_SET_RATE_PARENT,
1344 },
1345 },
1346};
1347
1348static struct clk_rcg sdc3_src = {

--- 16 unchanged lines hidden (view full) ---

1365 .parent_map = gcc_pxo_pll8_map,
1366 },
1367 .freq_tbl = clk_tbl_sdc,
1368 .clkr = {
1369 .enable_reg = 0x286c,
1370 .enable_mask = BIT(11),
1371 .hw.init = &(struct clk_init_data){
1372 .name = "sdc3_src",
1341 .parent_names = gcc_pxo_pll8,
1373 .parent_data = gcc_pxo_pll8,
1342 .num_parents = 2,
1343 .ops = &clk_rcg_ops,
1344 },
1345 }
1346};
1347
1348static struct clk_branch sdc3_clk = {
1349 .halt_reg = 0x2fc8,
1350 .halt_bit = 4,
1351 .clkr = {
1352 .enable_reg = 0x286c,
1353 .enable_mask = BIT(9),
1354 .hw.init = &(struct clk_init_data){
1355 .name = "sdc3_clk",
1374 .num_parents = 2,
1375 .ops = &clk_rcg_ops,
1376 },
1377 }
1378};
1379
1380static struct clk_branch sdc3_clk = {
1381 .halt_reg = 0x2fc8,
1382 .halt_bit = 4,
1383 .clkr = {
1384 .enable_reg = 0x286c,
1385 .enable_mask = BIT(9),
1386 .hw.init = &(struct clk_init_data){
1387 .name = "sdc3_clk",
1356 .parent_names = (const char *[]){ "sdc3_src" },
1388 .parent_hws = (const struct clk_hw*[]){
1389 &sdc3_src.clkr.hw,
1390 },
1357 .num_parents = 1,
1358 .ops = &clk_branch_ops,
1359 .flags = CLK_SET_RATE_PARENT,
1360 },
1361 },
1362};
1363
1364static struct clk_branch sdc1_h_clk = {

--- 51 unchanged lines hidden (view full) ---

1416 .parent_map = gcc_pxo_pll8_map,
1417 },
1418 .freq_tbl = clk_tbl_tsif_ref,
1419 .clkr = {
1420 .enable_reg = 0x2710,
1421 .enable_mask = BIT(11),
1422 .hw.init = &(struct clk_init_data){
1423 .name = "tsif_ref_src",
1391 .num_parents = 1,
1392 .ops = &clk_branch_ops,
1393 .flags = CLK_SET_RATE_PARENT,
1394 },
1395 },
1396};
1397
1398static struct clk_branch sdc1_h_clk = {

--- 51 unchanged lines hidden (view full) ---

1450 .parent_map = gcc_pxo_pll8_map,
1451 },
1452 .freq_tbl = clk_tbl_tsif_ref,
1453 .clkr = {
1454 .enable_reg = 0x2710,
1455 .enable_mask = BIT(11),
1456 .hw.init = &(struct clk_init_data){
1457 .name = "tsif_ref_src",
1424 .parent_names = gcc_pxo_pll8,
1458 .parent_data = gcc_pxo_pll8,
1425 .num_parents = 2,
1426 .ops = &clk_rcg_ops,
1427 },
1428 }
1429};
1430
1431static struct clk_branch tsif_ref_clk = {
1432 .halt_reg = 0x2fd4,
1433 .halt_bit = 5,
1434 .clkr = {
1435 .enable_reg = 0x2710,
1436 .enable_mask = BIT(9),
1437 .hw.init = &(struct clk_init_data){
1438 .name = "tsif_ref_clk",
1459 .num_parents = 2,
1460 .ops = &clk_rcg_ops,
1461 },
1462 }
1463};
1464
1465static struct clk_branch tsif_ref_clk = {
1466 .halt_reg = 0x2fd4,
1467 .halt_bit = 5,
1468 .clkr = {
1469 .enable_reg = 0x2710,
1470 .enable_mask = BIT(9),
1471 .hw.init = &(struct clk_init_data){
1472 .name = "tsif_ref_clk",
1439 .parent_names = (const char *[]){ "tsif_ref_src" },
1473 .parent_hws = (const struct clk_hw*[]){
1474 &tsif_ref_src.clkr.hw,
1475 },
1440 .num_parents = 1,
1441 .ops = &clk_branch_ops,
1442 .flags = CLK_SET_RATE_PARENT,
1443 },
1444 },
1445};
1446
1447static struct clk_branch tsif_h_clk = {

--- 130 unchanged lines hidden (view full) ---

1578 .parent_map = gcc_pxo_pll3_map,
1579 },
1580 .freq_tbl = clk_tbl_pcie_ref,
1581 .clkr = {
1582 .enable_reg = 0x3860,
1583 .enable_mask = BIT(11),
1584 .hw.init = &(struct clk_init_data){
1585 .name = "pcie_ref_src",
1476 .num_parents = 1,
1477 .ops = &clk_branch_ops,
1478 .flags = CLK_SET_RATE_PARENT,
1479 },
1480 },
1481};
1482
1483static struct clk_branch tsif_h_clk = {

--- 130 unchanged lines hidden (view full) ---

1614 .parent_map = gcc_pxo_pll3_map,
1615 },
1616 .freq_tbl = clk_tbl_pcie_ref,
1617 .clkr = {
1618 .enable_reg = 0x3860,
1619 .enable_mask = BIT(11),
1620 .hw.init = &(struct clk_init_data){
1621 .name = "pcie_ref_src",
1586 .parent_names = gcc_pxo_pll3,
1622 .parent_data = gcc_pxo_pll3,
1587 .num_parents = 2,
1588 .ops = &clk_rcg_ops,
1589 .flags = CLK_SET_RATE_GATE,
1590 },
1591 },
1592};
1593
1594static struct clk_branch pcie_ref_src_clk = {
1595 .halt_reg = 0x2fdc,
1596 .halt_bit = 30,
1597 .clkr = {
1598 .enable_reg = 0x3860,
1599 .enable_mask = BIT(9),
1600 .hw.init = &(struct clk_init_data){
1601 .name = "pcie_ref_src_clk",
1623 .num_parents = 2,
1624 .ops = &clk_rcg_ops,
1625 .flags = CLK_SET_RATE_GATE,
1626 },
1627 },
1628};
1629
1630static struct clk_branch pcie_ref_src_clk = {
1631 .halt_reg = 0x2fdc,
1632 .halt_bit = 30,
1633 .clkr = {
1634 .enable_reg = 0x3860,
1635 .enable_mask = BIT(9),
1636 .hw.init = &(struct clk_init_data){
1637 .name = "pcie_ref_src_clk",
1602 .parent_names = (const char *[]){ "pcie_ref_src" },
1638 .parent_hws = (const struct clk_hw*[]){
1639 &pcie_ref_src.clkr.hw,
1640 },
1603 .num_parents = 1,
1604 .ops = &clk_branch_ops,
1605 .flags = CLK_SET_RATE_PARENT,
1606 },
1607 },
1608};
1609
1610static struct clk_branch pcie_a_clk = {

--- 59 unchanged lines hidden (view full) ---

1670 .parent_map = gcc_pxo_pll3_map,
1671 },
1672 .freq_tbl = clk_tbl_pcie_ref,
1673 .clkr = {
1674 .enable_reg = 0x3aa0,
1675 .enable_mask = BIT(11),
1676 .hw.init = &(struct clk_init_data){
1677 .name = "pcie1_ref_src",
1641 .num_parents = 1,
1642 .ops = &clk_branch_ops,
1643 .flags = CLK_SET_RATE_PARENT,
1644 },
1645 },
1646};
1647
1648static struct clk_branch pcie_a_clk = {

--- 59 unchanged lines hidden (view full) ---

1708 .parent_map = gcc_pxo_pll3_map,
1709 },
1710 .freq_tbl = clk_tbl_pcie_ref,
1711 .clkr = {
1712 .enable_reg = 0x3aa0,
1713 .enable_mask = BIT(11),
1714 .hw.init = &(struct clk_init_data){
1715 .name = "pcie1_ref_src",
1678 .parent_names = gcc_pxo_pll3,
1716 .parent_data = gcc_pxo_pll3,
1679 .num_parents = 2,
1680 .ops = &clk_rcg_ops,
1681 .flags = CLK_SET_RATE_GATE,
1682 },
1683 },
1684};
1685
1686static struct clk_branch pcie1_ref_src_clk = {
1687 .halt_reg = 0x2fdc,
1688 .halt_bit = 27,
1689 .clkr = {
1690 .enable_reg = 0x3aa0,
1691 .enable_mask = BIT(9),
1692 .hw.init = &(struct clk_init_data){
1693 .name = "pcie1_ref_src_clk",
1717 .num_parents = 2,
1718 .ops = &clk_rcg_ops,
1719 .flags = CLK_SET_RATE_GATE,
1720 },
1721 },
1722};
1723
1724static struct clk_branch pcie1_ref_src_clk = {
1725 .halt_reg = 0x2fdc,
1726 .halt_bit = 27,
1727 .clkr = {
1728 .enable_reg = 0x3aa0,
1729 .enable_mask = BIT(9),
1730 .hw.init = &(struct clk_init_data){
1731 .name = "pcie1_ref_src_clk",
1694 .parent_names = (const char *[]){ "pcie1_ref_src" },
1732 .parent_hws = (const struct clk_hw*[]){
1733 &pcie1_ref_src.clkr.hw,
1734 },
1695 .num_parents = 1,
1696 .ops = &clk_branch_ops,
1697 .flags = CLK_SET_RATE_PARENT,
1698 },
1699 },
1700};
1701
1702static struct clk_branch pcie1_a_clk = {

--- 59 unchanged lines hidden (view full) ---

1762 .parent_map = gcc_pxo_pll3_map,
1763 },
1764 .freq_tbl = clk_tbl_pcie_ref,
1765 .clkr = {
1766 .enable_reg = 0x3ae0,
1767 .enable_mask = BIT(11),
1768 .hw.init = &(struct clk_init_data){
1769 .name = "pcie2_ref_src",
1735 .num_parents = 1,
1736 .ops = &clk_branch_ops,
1737 .flags = CLK_SET_RATE_PARENT,
1738 },
1739 },
1740};
1741
1742static struct clk_branch pcie1_a_clk = {

--- 59 unchanged lines hidden (view full) ---

1802 .parent_map = gcc_pxo_pll3_map,
1803 },
1804 .freq_tbl = clk_tbl_pcie_ref,
1805 .clkr = {
1806 .enable_reg = 0x3ae0,
1807 .enable_mask = BIT(11),
1808 .hw.init = &(struct clk_init_data){
1809 .name = "pcie2_ref_src",
1770 .parent_names = gcc_pxo_pll3,
1810 .parent_data = gcc_pxo_pll3,
1771 .num_parents = 2,
1772 .ops = &clk_rcg_ops,
1773 .flags = CLK_SET_RATE_GATE,
1774 },
1775 },
1776};
1777
1778static struct clk_branch pcie2_ref_src_clk = {
1779 .halt_reg = 0x2fdc,
1780 .halt_bit = 24,
1781 .clkr = {
1782 .enable_reg = 0x3ae0,
1783 .enable_mask = BIT(9),
1784 .hw.init = &(struct clk_init_data){
1785 .name = "pcie2_ref_src_clk",
1811 .num_parents = 2,
1812 .ops = &clk_rcg_ops,
1813 .flags = CLK_SET_RATE_GATE,
1814 },
1815 },
1816};
1817
1818static struct clk_branch pcie2_ref_src_clk = {
1819 .halt_reg = 0x2fdc,
1820 .halt_bit = 24,
1821 .clkr = {
1822 .enable_reg = 0x3ae0,
1823 .enable_mask = BIT(9),
1824 .hw.init = &(struct clk_init_data){
1825 .name = "pcie2_ref_src_clk",
1786 .parent_names = (const char *[]){ "pcie2_ref_src" },
1826 .parent_hws = (const struct clk_hw*[]){
1827 &pcie2_ref_src.clkr.hw,
1828 },
1787 .num_parents = 1,
1788 .ops = &clk_branch_ops,
1789 .flags = CLK_SET_RATE_PARENT,
1790 },
1791 },
1792};
1793
1794static struct clk_branch pcie2_a_clk = {

--- 64 unchanged lines hidden (view full) ---

1859 .parent_map = gcc_pxo_pll3_sata_map,
1860 },
1861 .freq_tbl = clk_tbl_sata_ref,
1862 .clkr = {
1863 .enable_reg = 0x2c08,
1864 .enable_mask = BIT(7),
1865 .hw.init = &(struct clk_init_data){
1866 .name = "sata_ref_src",
1829 .num_parents = 1,
1830 .ops = &clk_branch_ops,
1831 .flags = CLK_SET_RATE_PARENT,
1832 },
1833 },
1834};
1835
1836static struct clk_branch pcie2_a_clk = {

--- 64 unchanged lines hidden (view full) ---

1901 .parent_map = gcc_pxo_pll3_sata_map,
1902 },
1903 .freq_tbl = clk_tbl_sata_ref,
1904 .clkr = {
1905 .enable_reg = 0x2c08,
1906 .enable_mask = BIT(7),
1907 .hw.init = &(struct clk_init_data){
1908 .name = "sata_ref_src",
1867 .parent_names = gcc_pxo_pll3,
1909 .parent_data = gcc_pxo_pll3,
1868 .num_parents = 2,
1869 .ops = &clk_rcg_ops,
1870 .flags = CLK_SET_RATE_GATE,
1871 },
1872 },
1873};
1874
1875static struct clk_branch sata_rxoob_clk = {
1876 .halt_reg = 0x2fdc,
1877 .halt_bit = 20,
1878 .clkr = {
1879 .enable_reg = 0x2c0c,
1880 .enable_mask = BIT(4),
1881 .hw.init = &(struct clk_init_data){
1882 .name = "sata_rxoob_clk",
1910 .num_parents = 2,
1911 .ops = &clk_rcg_ops,
1912 .flags = CLK_SET_RATE_GATE,
1913 },
1914 },
1915};
1916
1917static struct clk_branch sata_rxoob_clk = {
1918 .halt_reg = 0x2fdc,
1919 .halt_bit = 20,
1920 .clkr = {
1921 .enable_reg = 0x2c0c,
1922 .enable_mask = BIT(4),
1923 .hw.init = &(struct clk_init_data){
1924 .name = "sata_rxoob_clk",
1883 .parent_names = (const char *[]){ "sata_ref_src" },
1925 .parent_hws = (const struct clk_hw*[]){
1926 &sata_ref_src.clkr.hw,
1927 },
1884 .num_parents = 1,
1885 .ops = &clk_branch_ops,
1886 .flags = CLK_SET_RATE_PARENT,
1887 },
1888 },
1889};
1890
1891static struct clk_branch sata_pmalive_clk = {
1892 .halt_reg = 0x2fdc,
1893 .halt_bit = 19,
1894 .clkr = {
1895 .enable_reg = 0x2c10,
1896 .enable_mask = BIT(4),
1897 .hw.init = &(struct clk_init_data){
1898 .name = "sata_pmalive_clk",
1928 .num_parents = 1,
1929 .ops = &clk_branch_ops,
1930 .flags = CLK_SET_RATE_PARENT,
1931 },
1932 },
1933};
1934
1935static struct clk_branch sata_pmalive_clk = {
1936 .halt_reg = 0x2fdc,
1937 .halt_bit = 19,
1938 .clkr = {
1939 .enable_reg = 0x2c10,
1940 .enable_mask = BIT(4),
1941 .hw.init = &(struct clk_init_data){
1942 .name = "sata_pmalive_clk",
1899 .parent_names = (const char *[]){ "sata_ref_src" },
1943 .parent_hws = (const struct clk_hw*[]){
1944 &sata_ref_src.clkr.hw,
1945 },
1900 .num_parents = 1,
1901 .ops = &clk_branch_ops,
1902 .flags = CLK_SET_RATE_PARENT,
1903 },
1904 },
1905};
1906
1907static struct clk_branch sata_phy_ref_clk = {
1908 .halt_reg = 0x2fdc,
1909 .halt_bit = 18,
1910 .clkr = {
1911 .enable_reg = 0x2c14,
1912 .enable_mask = BIT(4),
1913 .hw.init = &(struct clk_init_data){
1914 .name = "sata_phy_ref_clk",
1946 .num_parents = 1,
1947 .ops = &clk_branch_ops,
1948 .flags = CLK_SET_RATE_PARENT,
1949 },
1950 },
1951};
1952
1953static struct clk_branch sata_phy_ref_clk = {
1954 .halt_reg = 0x2fdc,
1955 .halt_bit = 18,
1956 .clkr = {
1957 .enable_reg = 0x2c14,
1958 .enable_mask = BIT(4),
1959 .hw.init = &(struct clk_init_data){
1960 .name = "sata_phy_ref_clk",
1915 .parent_names = (const char *[]){ "pxo" },
1961 .parent_data = gcc_pxo,
1916 .num_parents = 1,
1917 .ops = &clk_branch_ops,
1918 },
1919 },
1920};
1921
1922static struct clk_branch sata_a_clk = {
1923 .halt_reg = 0x2fc0,

--- 72 unchanged lines hidden (view full) ---

1996 .parent_map = gcc_pxo_pll8_pll0_map,
1997 },
1998 .freq_tbl = clk_tbl_usb30_master,
1999 .clkr = {
2000 .enable_reg = 0x3b2c,
2001 .enable_mask = BIT(11),
2002 .hw.init = &(struct clk_init_data){
2003 .name = "usb30_master_ref_src",
1962 .num_parents = 1,
1963 .ops = &clk_branch_ops,
1964 },
1965 },
1966};
1967
1968static struct clk_branch sata_a_clk = {
1969 .halt_reg = 0x2fc0,

--- 72 unchanged lines hidden (view full) ---

2042 .parent_map = gcc_pxo_pll8_pll0_map,
2043 },
2044 .freq_tbl = clk_tbl_usb30_master,
2045 .clkr = {
2046 .enable_reg = 0x3b2c,
2047 .enable_mask = BIT(11),
2048 .hw.init = &(struct clk_init_data){
2049 .name = "usb30_master_ref_src",
2004 .parent_names = gcc_pxo_pll8_pll0,
2050 .parent_data = gcc_pxo_pll8_pll0,
2005 .num_parents = 3,
2006 .ops = &clk_rcg_ops,
2007 .flags = CLK_SET_RATE_GATE,
2008 },
2009 },
2010};
2011
2012static struct clk_branch usb30_0_branch_clk = {
2013 .halt_reg = 0x2fc4,
2014 .halt_bit = 22,
2015 .clkr = {
2016 .enable_reg = 0x3b24,
2017 .enable_mask = BIT(4),
2018 .hw.init = &(struct clk_init_data){
2019 .name = "usb30_0_branch_clk",
2051 .num_parents = 3,
2052 .ops = &clk_rcg_ops,
2053 .flags = CLK_SET_RATE_GATE,
2054 },
2055 },
2056};
2057
2058static struct clk_branch usb30_0_branch_clk = {
2059 .halt_reg = 0x2fc4,
2060 .halt_bit = 22,
2061 .clkr = {
2062 .enable_reg = 0x3b24,
2063 .enable_mask = BIT(4),
2064 .hw.init = &(struct clk_init_data){
2065 .name = "usb30_0_branch_clk",
2020 .parent_names = (const char *[]){ "usb30_master_ref_src", },
2066 .parent_hws = (const struct clk_hw*[]){
2067 &usb30_master_clk_src.clkr.hw,
2068 },
2021 .num_parents = 1,
2022 .ops = &clk_branch_ops,
2023 .flags = CLK_SET_RATE_PARENT,
2024 },
2025 },
2026};
2027
2028static struct clk_branch usb30_1_branch_clk = {
2029 .halt_reg = 0x2fc4,
2030 .halt_bit = 17,
2031 .clkr = {
2032 .enable_reg = 0x3b34,
2033 .enable_mask = BIT(4),
2034 .hw.init = &(struct clk_init_data){
2035 .name = "usb30_1_branch_clk",
2069 .num_parents = 1,
2070 .ops = &clk_branch_ops,
2071 .flags = CLK_SET_RATE_PARENT,
2072 },
2073 },
2074};
2075
2076static struct clk_branch usb30_1_branch_clk = {
2077 .halt_reg = 0x2fc4,
2078 .halt_bit = 17,
2079 .clkr = {
2080 .enable_reg = 0x3b34,
2081 .enable_mask = BIT(4),
2082 .hw.init = &(struct clk_init_data){
2083 .name = "usb30_1_branch_clk",
2036 .parent_names = (const char *[]){ "usb30_master_ref_src", },
2084 .parent_hws = (const struct clk_hw*[]){
2085 &usb30_master_clk_src.clkr.hw,
2086 },
2037 .num_parents = 1,
2038 .ops = &clk_branch_ops,
2039 .flags = CLK_SET_RATE_PARENT,
2040 },
2041 },
2042};
2043
2044static const struct freq_tbl clk_tbl_usb30_utmi[] = {

--- 21 unchanged lines hidden (view full) ---

2066 .parent_map = gcc_pxo_pll8_pll0_map,
2067 },
2068 .freq_tbl = clk_tbl_usb30_utmi,
2069 .clkr = {
2070 .enable_reg = 0x3b44,
2071 .enable_mask = BIT(11),
2072 .hw.init = &(struct clk_init_data){
2073 .name = "usb30_utmi_clk",
2087 .num_parents = 1,
2088 .ops = &clk_branch_ops,
2089 .flags = CLK_SET_RATE_PARENT,
2090 },
2091 },
2092};
2093
2094static const struct freq_tbl clk_tbl_usb30_utmi[] = {

--- 21 unchanged lines hidden (view full) ---

2116 .parent_map = gcc_pxo_pll8_pll0_map,
2117 },
2118 .freq_tbl = clk_tbl_usb30_utmi,
2119 .clkr = {
2120 .enable_reg = 0x3b44,
2121 .enable_mask = BIT(11),
2122 .hw.init = &(struct clk_init_data){
2123 .name = "usb30_utmi_clk",
2074 .parent_names = gcc_pxo_pll8_pll0,
2124 .parent_data = gcc_pxo_pll8_pll0,
2075 .num_parents = 3,
2076 .ops = &clk_rcg_ops,
2077 .flags = CLK_SET_RATE_GATE,
2078 },
2079 },
2080};
2081
2082static struct clk_branch usb30_0_utmi_clk_ctl = {
2083 .halt_reg = 0x2fc4,
2084 .halt_bit = 21,
2085 .clkr = {
2086 .enable_reg = 0x3b48,
2087 .enable_mask = BIT(4),
2088 .hw.init = &(struct clk_init_data){
2089 .name = "usb30_0_utmi_clk_ctl",
2125 .num_parents = 3,
2126 .ops = &clk_rcg_ops,
2127 .flags = CLK_SET_RATE_GATE,
2128 },
2129 },
2130};
2131
2132static struct clk_branch usb30_0_utmi_clk_ctl = {
2133 .halt_reg = 0x2fc4,
2134 .halt_bit = 21,
2135 .clkr = {
2136 .enable_reg = 0x3b48,
2137 .enable_mask = BIT(4),
2138 .hw.init = &(struct clk_init_data){
2139 .name = "usb30_0_utmi_clk_ctl",
2090 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2140 .parent_hws = (const struct clk_hw*[]){
2141 &usb30_utmi_clk.clkr.hw,
2142 },
2091 .num_parents = 1,
2092 .ops = &clk_branch_ops,
2093 .flags = CLK_SET_RATE_PARENT,
2094 },
2095 },
2096};
2097
2098static struct clk_branch usb30_1_utmi_clk_ctl = {
2099 .halt_reg = 0x2fc4,
2100 .halt_bit = 15,
2101 .clkr = {
2102 .enable_reg = 0x3b4c,
2103 .enable_mask = BIT(4),
2104 .hw.init = &(struct clk_init_data){
2105 .name = "usb30_1_utmi_clk_ctl",
2143 .num_parents = 1,
2144 .ops = &clk_branch_ops,
2145 .flags = CLK_SET_RATE_PARENT,
2146 },
2147 },
2148};
2149
2150static struct clk_branch usb30_1_utmi_clk_ctl = {
2151 .halt_reg = 0x2fc4,
2152 .halt_bit = 15,
2153 .clkr = {
2154 .enable_reg = 0x3b4c,
2155 .enable_mask = BIT(4),
2156 .hw.init = &(struct clk_init_data){
2157 .name = "usb30_1_utmi_clk_ctl",
2106 .parent_names = (const char *[]){ "usb30_utmi_clk", },
2158 .parent_hws = (const struct clk_hw*[]){
2159 &usb30_utmi_clk.clkr.hw,
2160 },
2107 .num_parents = 1,
2108 .ops = &clk_branch_ops,
2109 .flags = CLK_SET_RATE_PARENT,
2110 },
2111 },
2112};
2113
2114static const struct freq_tbl clk_tbl_usb[] = {

--- 21 unchanged lines hidden (view full) ---

2136 .parent_map = gcc_pxo_pll8_pll0_map,
2137 },
2138 .freq_tbl = clk_tbl_usb,
2139 .clkr = {
2140 .enable_reg = 0x2968,
2141 .enable_mask = BIT(11),
2142 .hw.init = &(struct clk_init_data){
2143 .name = "usb_hs1_xcvr_src",
2161 .num_parents = 1,
2162 .ops = &clk_branch_ops,
2163 .flags = CLK_SET_RATE_PARENT,
2164 },
2165 },
2166};
2167
2168static const struct freq_tbl clk_tbl_usb[] = {

--- 21 unchanged lines hidden (view full) ---

2190 .parent_map = gcc_pxo_pll8_pll0_map,
2191 },
2192 .freq_tbl = clk_tbl_usb,
2193 .clkr = {
2194 .enable_reg = 0x2968,
2195 .enable_mask = BIT(11),
2196 .hw.init = &(struct clk_init_data){
2197 .name = "usb_hs1_xcvr_src",
2144 .parent_names = gcc_pxo_pll8_pll0,
2198 .parent_data = gcc_pxo_pll8_pll0,
2145 .num_parents = 3,
2146 .ops = &clk_rcg_ops,
2147 .flags = CLK_SET_RATE_GATE,
2148 },
2149 },
2150};
2151
2152static struct clk_branch usb_hs1_xcvr_clk = {
2153 .halt_reg = 0x2fcc,
2154 .halt_bit = 17,
2155 .clkr = {
2156 .enable_reg = 0x290c,
2157 .enable_mask = BIT(9),
2158 .hw.init = &(struct clk_init_data){
2159 .name = "usb_hs1_xcvr_clk",
2199 .num_parents = 3,
2200 .ops = &clk_rcg_ops,
2201 .flags = CLK_SET_RATE_GATE,
2202 },
2203 },
2204};
2205
2206static struct clk_branch usb_hs1_xcvr_clk = {
2207 .halt_reg = 0x2fcc,
2208 .halt_bit = 17,
2209 .clkr = {
2210 .enable_reg = 0x290c,
2211 .enable_mask = BIT(9),
2212 .hw.init = &(struct clk_init_data){
2213 .name = "usb_hs1_xcvr_clk",
2160 .parent_names = (const char *[]){ "usb_hs1_xcvr_src" },
2214 .parent_hws = (const struct clk_hw*[]){
2215 &usb_hs1_xcvr_clk_src.clkr.hw,
2216 },
2161 .num_parents = 1,
2162 .ops = &clk_branch_ops,
2163 .flags = CLK_SET_RATE_PARENT,
2164 },
2165 },
2166};
2167
2168static struct clk_branch usb_hs1_h_clk = {

--- 31 unchanged lines hidden (view full) ---

2200 .parent_map = gcc_pxo_pll8_pll0_map,
2201 },
2202 .freq_tbl = clk_tbl_usb,
2203 .clkr = {
2204 .enable_reg = 0x2968,
2205 .enable_mask = BIT(11),
2206 .hw.init = &(struct clk_init_data){
2207 .name = "usb_fs1_xcvr_src",
2217 .num_parents = 1,
2218 .ops = &clk_branch_ops,
2219 .flags = CLK_SET_RATE_PARENT,
2220 },
2221 },
2222};
2223
2224static struct clk_branch usb_hs1_h_clk = {

--- 31 unchanged lines hidden (view full) ---

2256 .parent_map = gcc_pxo_pll8_pll0_map,
2257 },
2258 .freq_tbl = clk_tbl_usb,
2259 .clkr = {
2260 .enable_reg = 0x2968,
2261 .enable_mask = BIT(11),
2262 .hw.init = &(struct clk_init_data){
2263 .name = "usb_fs1_xcvr_src",
2208 .parent_names = gcc_pxo_pll8_pll0,
2264 .parent_data = gcc_pxo_pll8_pll0,
2209 .num_parents = 3,
2210 .ops = &clk_rcg_ops,
2211 .flags = CLK_SET_RATE_GATE,
2212 },
2213 },
2214};
2215
2216static struct clk_branch usb_fs1_xcvr_clk = {
2217 .halt_reg = 0x2fcc,
2218 .halt_bit = 17,
2219 .clkr = {
2220 .enable_reg = 0x2968,
2221 .enable_mask = BIT(9),
2222 .hw.init = &(struct clk_init_data){
2223 .name = "usb_fs1_xcvr_clk",
2265 .num_parents = 3,
2266 .ops = &clk_rcg_ops,
2267 .flags = CLK_SET_RATE_GATE,
2268 },
2269 },
2270};
2271
2272static struct clk_branch usb_fs1_xcvr_clk = {
2273 .halt_reg = 0x2fcc,
2274 .halt_bit = 17,
2275 .clkr = {
2276 .enable_reg = 0x2968,
2277 .enable_mask = BIT(9),
2278 .hw.init = &(struct clk_init_data){
2279 .name = "usb_fs1_xcvr_clk",
2224 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2280 .parent_hws = (const struct clk_hw*[]){
2281 &usb_fs1_xcvr_clk_src.clkr.hw,
2282 },
2225 .num_parents = 1,
2226 .ops = &clk_branch_ops,
2227 .flags = CLK_SET_RATE_PARENT,
2228 },
2229 },
2230};
2231
2232static struct clk_branch usb_fs1_sys_clk = {
2233 .halt_reg = 0x2fcc,
2234 .halt_bit = 18,
2235 .clkr = {
2236 .enable_reg = 0x296c,
2237 .enable_mask = BIT(4),
2238 .hw.init = &(struct clk_init_data){
2239 .name = "usb_fs1_sys_clk",
2283 .num_parents = 1,
2284 .ops = &clk_branch_ops,
2285 .flags = CLK_SET_RATE_PARENT,
2286 },
2287 },
2288};
2289
2290static struct clk_branch usb_fs1_sys_clk = {
2291 .halt_reg = 0x2fcc,
2292 .halt_bit = 18,
2293 .clkr = {
2294 .enable_reg = 0x296c,
2295 .enable_mask = BIT(4),
2296 .hw.init = &(struct clk_init_data){
2297 .name = "usb_fs1_sys_clk",
2240 .parent_names = (const char *[]){ "usb_fs1_xcvr_src", },
2298 .parent_hws = (const struct clk_hw*[]){
2299 &usb_fs1_xcvr_clk_src.clkr.hw,
2300 },
2241 .num_parents = 1,
2242 .ops = &clk_branch_ops,
2243 .flags = CLK_SET_RATE_PARENT,
2244 },
2245 },
2246};
2247
2248static struct clk_branch usb_fs1_h_clk = {

--- 83 unchanged lines hidden (view full) ---

2332 },
2333 .mux_sel_bit = 0,
2334 .freq_tbl = clk_tbl_gmac,
2335 .clkr = {
2336 .enable_reg = 0x3ca0,
2337 .enable_mask = BIT(1),
2338 .hw.init = &(struct clk_init_data){
2339 .name = "gmac_core1_src",
2301 .num_parents = 1,
2302 .ops = &clk_branch_ops,
2303 .flags = CLK_SET_RATE_PARENT,
2304 },
2305 },
2306};
2307
2308static struct clk_branch usb_fs1_h_clk = {

--- 83 unchanged lines hidden (view full) ---

2392 },
2393 .mux_sel_bit = 0,
2394 .freq_tbl = clk_tbl_gmac,
2395 .clkr = {
2396 .enable_reg = 0x3ca0,
2397 .enable_mask = BIT(1),
2398 .hw.init = &(struct clk_init_data){
2399 .name = "gmac_core1_src",
2340 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2400 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2341 .num_parents = 5,
2342 .ops = &clk_dyn_rcg_ops,
2343 },
2344 },
2345};
2346
2347static struct clk_branch gmac_core1_clk = {
2348 .halt_reg = 0x3c20,
2349 .halt_bit = 4,
2350 .hwcg_reg = 0x3cb4,
2351 .hwcg_bit = 6,
2352 .clkr = {
2353 .enable_reg = 0x3cb4,
2354 .enable_mask = BIT(4),
2355 .hw.init = &(struct clk_init_data){
2356 .name = "gmac_core1_clk",
2401 .num_parents = 5,
2402 .ops = &clk_dyn_rcg_ops,
2403 },
2404 },
2405};
2406
2407static struct clk_branch gmac_core1_clk = {
2408 .halt_reg = 0x3c20,
2409 .halt_bit = 4,
2410 .hwcg_reg = 0x3cb4,
2411 .hwcg_bit = 6,
2412 .clkr = {
2413 .enable_reg = 0x3cb4,
2414 .enable_mask = BIT(4),
2415 .hw.init = &(struct clk_init_data){
2416 .name = "gmac_core1_clk",
2357 .parent_names = (const char *[]){
2358 "gmac_core1_src",
2417 .parent_hws = (const struct clk_hw*[]){
2418 &gmac_core1_src.clkr.hw,
2359 },
2360 .num_parents = 1,
2361 .ops = &clk_branch_ops,
2362 .flags = CLK_SET_RATE_PARENT,
2363 },
2364 },
2365};
2366

--- 37 unchanged lines hidden (view full) ---

2404 },
2405 .mux_sel_bit = 0,
2406 .freq_tbl = clk_tbl_gmac,
2407 .clkr = {
2408 .enable_reg = 0x3cc0,
2409 .enable_mask = BIT(1),
2410 .hw.init = &(struct clk_init_data){
2411 .name = "gmac_core2_src",
2419 },
2420 .num_parents = 1,
2421 .ops = &clk_branch_ops,
2422 .flags = CLK_SET_RATE_PARENT,
2423 },
2424 },
2425};
2426

--- 37 unchanged lines hidden (view full) ---

2464 },
2465 .mux_sel_bit = 0,
2466 .freq_tbl = clk_tbl_gmac,
2467 .clkr = {
2468 .enable_reg = 0x3cc0,
2469 .enable_mask = BIT(1),
2470 .hw.init = &(struct clk_init_data){
2471 .name = "gmac_core2_src",
2412 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2472 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2413 .num_parents = 5,
2414 .ops = &clk_dyn_rcg_ops,
2415 },
2416 },
2417};
2418
2419static struct clk_branch gmac_core2_clk = {
2420 .halt_reg = 0x3c20,
2421 .halt_bit = 5,
2422 .hwcg_reg = 0x3cd4,
2423 .hwcg_bit = 6,
2424 .clkr = {
2425 .enable_reg = 0x3cd4,
2426 .enable_mask = BIT(4),
2427 .hw.init = &(struct clk_init_data){
2428 .name = "gmac_core2_clk",
2473 .num_parents = 5,
2474 .ops = &clk_dyn_rcg_ops,
2475 },
2476 },
2477};
2478
2479static struct clk_branch gmac_core2_clk = {
2480 .halt_reg = 0x3c20,
2481 .halt_bit = 5,
2482 .hwcg_reg = 0x3cd4,
2483 .hwcg_bit = 6,
2484 .clkr = {
2485 .enable_reg = 0x3cd4,
2486 .enable_mask = BIT(4),
2487 .hw.init = &(struct clk_init_data){
2488 .name = "gmac_core2_clk",
2429 .parent_names = (const char *[]){
2430 "gmac_core2_src",
2489 .parent_hws = (const struct clk_hw*[]){
2490 &gmac_core2_src.clkr.hw,
2431 },
2432 .num_parents = 1,
2433 .ops = &clk_branch_ops,
2434 .flags = CLK_SET_RATE_PARENT,
2435 },
2436 },
2437};
2438

--- 37 unchanged lines hidden (view full) ---

2476 },
2477 .mux_sel_bit = 0,
2478 .freq_tbl = clk_tbl_gmac,
2479 .clkr = {
2480 .enable_reg = 0x3ce0,
2481 .enable_mask = BIT(1),
2482 .hw.init = &(struct clk_init_data){
2483 .name = "gmac_core3_src",
2491 },
2492 .num_parents = 1,
2493 .ops = &clk_branch_ops,
2494 .flags = CLK_SET_RATE_PARENT,
2495 },
2496 },
2497};
2498

--- 37 unchanged lines hidden (view full) ---

2536 },
2537 .mux_sel_bit = 0,
2538 .freq_tbl = clk_tbl_gmac,
2539 .clkr = {
2540 .enable_reg = 0x3ce0,
2541 .enable_mask = BIT(1),
2542 .hw.init = &(struct clk_init_data){
2543 .name = "gmac_core3_src",
2484 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2544 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2485 .num_parents = 5,
2486 .ops = &clk_dyn_rcg_ops,
2487 },
2488 },
2489};
2490
2491static struct clk_branch gmac_core3_clk = {
2492 .halt_reg = 0x3c20,
2493 .halt_bit = 6,
2494 .hwcg_reg = 0x3cf4,
2495 .hwcg_bit = 6,
2496 .clkr = {
2497 .enable_reg = 0x3cf4,
2498 .enable_mask = BIT(4),
2499 .hw.init = &(struct clk_init_data){
2500 .name = "gmac_core3_clk",
2545 .num_parents = 5,
2546 .ops = &clk_dyn_rcg_ops,
2547 },
2548 },
2549};
2550
2551static struct clk_branch gmac_core3_clk = {
2552 .halt_reg = 0x3c20,
2553 .halt_bit = 6,
2554 .hwcg_reg = 0x3cf4,
2555 .hwcg_bit = 6,
2556 .clkr = {
2557 .enable_reg = 0x3cf4,
2558 .enable_mask = BIT(4),
2559 .hw.init = &(struct clk_init_data){
2560 .name = "gmac_core3_clk",
2501 .parent_names = (const char *[]){
2502 "gmac_core3_src",
2561 .parent_hws = (const struct clk_hw*[]){
2562 &gmac_core3_src.clkr.hw,
2503 },
2504 .num_parents = 1,
2505 .ops = &clk_branch_ops,
2506 .flags = CLK_SET_RATE_PARENT,
2507 },
2508 },
2509};
2510

--- 37 unchanged lines hidden (view full) ---

2548 },
2549 .mux_sel_bit = 0,
2550 .freq_tbl = clk_tbl_gmac,
2551 .clkr = {
2552 .enable_reg = 0x3d00,
2553 .enable_mask = BIT(1),
2554 .hw.init = &(struct clk_init_data){
2555 .name = "gmac_core4_src",
2563 },
2564 .num_parents = 1,
2565 .ops = &clk_branch_ops,
2566 .flags = CLK_SET_RATE_PARENT,
2567 },
2568 },
2569};
2570

--- 37 unchanged lines hidden (view full) ---

2608 },
2609 .mux_sel_bit = 0,
2610 .freq_tbl = clk_tbl_gmac,
2611 .clkr = {
2612 .enable_reg = 0x3d00,
2613 .enable_mask = BIT(1),
2614 .hw.init = &(struct clk_init_data){
2615 .name = "gmac_core4_src",
2556 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2616 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2557 .num_parents = 5,
2558 .ops = &clk_dyn_rcg_ops,
2559 },
2560 },
2561};
2562
2563static struct clk_branch gmac_core4_clk = {
2564 .halt_reg = 0x3c20,
2565 .halt_bit = 7,
2566 .hwcg_reg = 0x3d14,
2567 .hwcg_bit = 6,
2568 .clkr = {
2569 .enable_reg = 0x3d14,
2570 .enable_mask = BIT(4),
2571 .hw.init = &(struct clk_init_data){
2572 .name = "gmac_core4_clk",
2617 .num_parents = 5,
2618 .ops = &clk_dyn_rcg_ops,
2619 },
2620 },
2621};
2622
2623static struct clk_branch gmac_core4_clk = {
2624 .halt_reg = 0x3c20,
2625 .halt_bit = 7,
2626 .hwcg_reg = 0x3d14,
2627 .hwcg_bit = 6,
2628 .clkr = {
2629 .enable_reg = 0x3d14,
2630 .enable_mask = BIT(4),
2631 .hw.init = &(struct clk_init_data){
2632 .name = "gmac_core4_clk",
2573 .parent_names = (const char *[]){
2574 "gmac_core4_src",
2633 .parent_hws = (const struct clk_hw*[]){
2634 &gmac_core4_src.clkr.hw,
2575 },
2576 .num_parents = 1,
2577 .ops = &clk_branch_ops,
2578 .flags = CLK_SET_RATE_PARENT,
2579 },
2580 },
2581};
2582

--- 25 unchanged lines hidden (view full) ---

2608 },
2609 .mux_sel_bit = 0,
2610 .freq_tbl = clk_tbl_nss_tcm,
2611 .clkr = {
2612 .enable_reg = 0x3dc0,
2613 .enable_mask = BIT(1),
2614 .hw.init = &(struct clk_init_data){
2615 .name = "nss_tcm_src",
2635 },
2636 .num_parents = 1,
2637 .ops = &clk_branch_ops,
2638 .flags = CLK_SET_RATE_PARENT,
2639 },
2640 },
2641};
2642

--- 25 unchanged lines hidden (view full) ---

2668 },
2669 .mux_sel_bit = 0,
2670 .freq_tbl = clk_tbl_nss_tcm,
2671 .clkr = {
2672 .enable_reg = 0x3dc0,
2673 .enable_mask = BIT(1),
2674 .hw.init = &(struct clk_init_data){
2675 .name = "nss_tcm_src",
2616 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2676 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2617 .num_parents = 5,
2618 .ops = &clk_dyn_rcg_ops,
2619 },
2620 },
2621};
2622
2623static struct clk_branch nss_tcm_clk = {
2624 .halt_reg = 0x3c20,
2625 .halt_bit = 14,
2626 .clkr = {
2627 .enable_reg = 0x3dd0,
2628 .enable_mask = BIT(6) | BIT(4),
2629 .hw.init = &(struct clk_init_data){
2630 .name = "nss_tcm_clk",
2677 .num_parents = 5,
2678 .ops = &clk_dyn_rcg_ops,
2679 },
2680 },
2681};
2682
2683static struct clk_branch nss_tcm_clk = {
2684 .halt_reg = 0x3c20,
2685 .halt_bit = 14,
2686 .clkr = {
2687 .enable_reg = 0x3dd0,
2688 .enable_mask = BIT(6) | BIT(4),
2689 .hw.init = &(struct clk_init_data){
2690 .name = "nss_tcm_clk",
2631 .parent_names = (const char *[]){
2632 "nss_tcm_src",
2691 .parent_hws = (const struct clk_hw*[]){
2692 &nss_tcm_src.clkr.hw,
2633 },
2634 .num_parents = 1,
2635 .ops = &clk_branch_ops,
2636 .flags = CLK_SET_RATE_PARENT,
2637 },
2638 },
2639};
2640

--- 45 unchanged lines hidden (view full) ---

2686 },
2687 .mux_sel_bit = 0,
2688 .freq_tbl = clk_tbl_nss,
2689 .clkr = {
2690 .enable_reg = 0x3d20,
2691 .enable_mask = BIT(1),
2692 .hw.init = &(struct clk_init_data){
2693 .name = "ubi32_core1_src_clk",
2693 },
2694 .num_parents = 1,
2695 .ops = &clk_branch_ops,
2696 .flags = CLK_SET_RATE_PARENT,
2697 },
2698 },
2699};
2700

--- 45 unchanged lines hidden (view full) ---

2746 },
2747 .mux_sel_bit = 0,
2748 .freq_tbl = clk_tbl_nss,
2749 .clkr = {
2750 .enable_reg = 0x3d20,
2751 .enable_mask = BIT(1),
2752 .hw.init = &(struct clk_init_data){
2753 .name = "ubi32_core1_src_clk",
2694 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2754 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2695 .num_parents = 5,
2696 .ops = &clk_dyn_rcg_ops,
2697 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2698 },
2699 },
2700};
2701
2702static struct clk_dyn_rcg ubi32_core2_src_clk = {

--- 36 unchanged lines hidden (view full) ---

2739 },
2740 .mux_sel_bit = 0,
2741 .freq_tbl = clk_tbl_nss,
2742 .clkr = {
2743 .enable_reg = 0x3d40,
2744 .enable_mask = BIT(1),
2745 .hw.init = &(struct clk_init_data){
2746 .name = "ubi32_core2_src_clk",
2755 .num_parents = 5,
2756 .ops = &clk_dyn_rcg_ops,
2757 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2758 },
2759 },
2760};
2761
2762static struct clk_dyn_rcg ubi32_core2_src_clk = {

--- 36 unchanged lines hidden (view full) ---

2799 },
2800 .mux_sel_bit = 0,
2801 .freq_tbl = clk_tbl_nss,
2802 .clkr = {
2803 .enable_reg = 0x3d40,
2804 .enable_mask = BIT(1),
2805 .hw.init = &(struct clk_init_data){
2806 .name = "ubi32_core2_src_clk",
2747 .parent_names = gcc_pxo_pll8_pll14_pll18_pll0,
2807 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2748 .num_parents = 5,
2749 .ops = &clk_dyn_rcg_ops,
2750 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2751 },
2752 },
2753};
2754
2755static struct clk_regmap *gcc_ipq806x_clks[] = {

--- 362 unchanged lines hidden --- 		2808 .num_parents = 5,
2809 .ops = &clk_dyn_rcg_ops,
2810 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2811 },
2812 },
2813};
2814
2815static struct clk_regmap *gcc_ipq806x_clks[] = {

--- 362 unchanged lines hidden ---