gcc-ipq806x.c (7e726f34c782b2ca28a29ca9870e34e4319d65bc) gcc-ipq806x.c (b293510f3961b90dcab59965f57779be93ceda7c)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>

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251 .clkr.hw.init = &(struct clk_init_data){
252 .name = "pll18",
253 .parent_data = gcc_pxo,
254 .num_parents = 1,
255 .ops = &clk_pll_ops,
256 },
257};
258
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2014, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/kernel.h>
7#include <linux/bitops.h>
8#include <linux/err.h>

--- 242 unchanged lines hidden (view full) ---

251 .clkr.hw.init = &(struct clk_init_data){
252 .name = "pll18",
253 .parent_data = gcc_pxo,
254 .num_parents = 1,
255 .ops = &clk_pll_ops,
256 },
257};
258
259static struct clk_pll pll11 = {
260 .l_reg = 0x3184,
261 .m_reg = 0x3188,
262 .n_reg = 0x318c,
263 .config_reg = 0x3194,
264 .mode_reg = 0x3180,
265 .status_reg = 0x3198,
266 .status_bit = 16,
267 .clkr.hw.init = &(struct clk_init_data){
268 .name = "pll11",
269 .parent_data = &(const struct clk_parent_data){
270 .fw_name = "pxo",
271 },
272 .num_parents = 1,
273 .ops = &clk_pll_ops,
274 },
275};
276
259enum {
260 P_PXO,
261 P_PLL8,
262 P_PLL3,
263 P_PLL0,
264 P_CXO,
265 P_PLL14,
266 P_PLL18,
277enum {
278 P_PXO,
279 P_PLL8,
280 P_PLL3,
281 P_PLL0,
282 P_CXO,
283 P_PLL14,
284 P_PLL18,
285 P_PLL11,
267};
268
269static const struct parent_map gcc_pxo_pll8_map[] = {
270 { P_PXO, 0 },
271 { P_PLL8, 3 }
272};
273
274static const struct clk_parent_data gcc_pxo_pll8[] = {

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326static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
327 { .fw_name = "pxo", .name = "pxo" },
328 { .hw = &pll8_vote.hw },
329 { .hw = &pll0_vote.hw },
330 { .hw = &pll14.clkr.hw },
331 { .hw = &pll18.clkr.hw },
332};
333
286};
287
288static const struct parent_map gcc_pxo_pll8_map[] = {
289 { P_PXO, 0 },
290 { P_PLL8, 3 }
291};
292
293static const struct clk_parent_data gcc_pxo_pll8[] = {

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345static const struct clk_parent_data gcc_pxo_pll8_pll14_pll18_pll0[] = {
346 { .fw_name = "pxo", .name = "pxo" },
347 { .hw = &pll8_vote.hw },
348 { .hw = &pll0_vote.hw },
349 { .hw = &pll14.clkr.hw },
350 { .hw = &pll18.clkr.hw },
351};
352
353static const struct parent_map gcc_pxo_pll8_pll0_pll14_pll18_pll11_map[] = {
354 { P_PXO, 0 },
355 { P_PLL8, 4 },
356 { P_PLL0, 2 },
357 { P_PLL14, 5 },
358 { P_PLL18, 1 },
359 { P_PLL11, 3 },
360};
361
362static const struct clk_parent_data gcc_pxo_pll8_pll0_pll14_pll18_pll11[] = {
363 { .fw_name = "pxo" },
364 { .hw = &pll8_vote.hw },
365 { .hw = &pll0_vote.hw },
366 { .hw = &pll14.clkr.hw },
367 { .hw = &pll18.clkr.hw },
368 { .hw = &pll11.clkr.hw },
369
370};
371
372static const struct parent_map gcc_pxo_pll3_pll0_pll14_pll18_pll11_map[] = {
373 { P_PXO, 0 },
374 { P_PLL3, 6 },
375 { P_PLL0, 2 },
376 { P_PLL14, 5 },
377 { P_PLL18, 1 },
378 { P_PLL11, 3 },
379};
380
381static const struct clk_parent_data gcc_pxo_pll3_pll0_pll14_pll18_pll11[] = {
382 { .fw_name = "pxo" },
383 { .hw = &pll3.clkr.hw },
384 { .hw = &pll0_vote.hw },
385 { .hw = &pll14.clkr.hw },
386 { .hw = &pll18.clkr.hw },
387 { .hw = &pll11.clkr.hw },
388
389};
390
334static struct freq_tbl clk_tbl_gsbi_uart[] = {
335 { 1843200, P_PLL8, 2, 6, 625 },
336 { 3686400, P_PLL8, 2, 12, 625 },
337 { 7372800, P_PLL8, 2, 24, 625 },
338 { 14745600, P_PLL8, 2, 48, 625 },
339 { 16000000, P_PLL8, 4, 1, 6 },
340 { 24000000, P_PLL8, 4, 1, 4 },
341 { 32000000, P_PLL8, 4, 1, 3 },

--- 2477 unchanged lines hidden (view full) ---

2819 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2820 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2821 .ops = &clk_dyn_rcg_ops,
2822 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2823 },
2824 },
2825};
2826
391static struct freq_tbl clk_tbl_gsbi_uart[] = {
392 { 1843200, P_PLL8, 2, 6, 625 },
393 { 3686400, P_PLL8, 2, 12, 625 },
394 { 7372800, P_PLL8, 2, 24, 625 },
395 { 14745600, P_PLL8, 2, 48, 625 },
396 { 16000000, P_PLL8, 4, 1, 6 },
397 { 24000000, P_PLL8, 4, 1, 4 },
398 { 32000000, P_PLL8, 4, 1, 3 },

--- 2477 unchanged lines hidden (view full) ---

2876 .parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
2877 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
2878 .ops = &clk_dyn_rcg_ops,
2879 .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
2880 },
2881 },
2882};
2883
2884static const struct freq_tbl clk_tbl_ce5_core[] = {
2885 { 150000000, P_PLL3, 8, 1, 1 },
2886 { 213200000, P_PLL11, 5, 1, 1 },
2887 { }
2888};
2889
2890static struct clk_dyn_rcg ce5_core_src = {
2891 .ns_reg[0] = 0x36C4,
2892 .ns_reg[1] = 0x36C8,
2893 .bank_reg = 0x36C0,
2894 .s[0] = {
2895 .src_sel_shift = 0,
2896 .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
2897 },
2898 .s[1] = {
2899 .src_sel_shift = 0,
2900 .parent_map = gcc_pxo_pll3_pll0_pll14_pll18_pll11_map,
2901 },
2902 .p[0] = {
2903 .pre_div_shift = 3,
2904 .pre_div_width = 4,
2905 },
2906 .p[1] = {
2907 .pre_div_shift = 3,
2908 .pre_div_width = 4,
2909 },
2910 .mux_sel_bit = 0,
2911 .freq_tbl = clk_tbl_ce5_core,
2912 .clkr = {
2913 .enable_reg = 0x36C0,
2914 .enable_mask = BIT(1),
2915 .hw.init = &(struct clk_init_data){
2916 .name = "ce5_core_src",
2917 .parent_data = gcc_pxo_pll3_pll0_pll14_pll18_pll11,
2918 .num_parents = ARRAY_SIZE(gcc_pxo_pll3_pll0_pll14_pll18_pll11),
2919 .ops = &clk_dyn_rcg_ops,
2920 },
2921 },
2922};
2923
2924static struct clk_branch ce5_core_clk = {
2925 .halt_reg = 0x2FDC,
2926 .halt_bit = 5,
2927 .hwcg_reg = 0x36CC,
2928 .hwcg_bit = 6,
2929 .clkr = {
2930 .enable_reg = 0x36CC,
2931 .enable_mask = BIT(4),
2932 .hw.init = &(struct clk_init_data){
2933 .name = "ce5_core_clk",
2934 .parent_hws = (const struct clk_hw*[]){
2935 &ce5_core_src.clkr.hw,
2936 },
2937 .num_parents = 1,
2938 .ops = &clk_branch_ops,
2939 .flags = CLK_SET_RATE_PARENT,
2940 },
2941 },
2942};
2943
2944static const struct freq_tbl clk_tbl_ce5_a_clk[] = {
2945 { 160000000, P_PLL0, 5, 1, 1 },
2946 { 213200000, P_PLL11, 5, 1, 1 },
2947 { }
2948};
2949
2950static struct clk_dyn_rcg ce5_a_clk_src = {
2951 .ns_reg[0] = 0x3d84,
2952 .ns_reg[1] = 0x3d88,
2953 .bank_reg = 0x3d80,
2954 .s[0] = {
2955 .src_sel_shift = 0,
2956 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
2957 },
2958 .s[1] = {
2959 .src_sel_shift = 0,
2960 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
2961 },
2962 .p[0] = {
2963 .pre_div_shift = 3,
2964 .pre_div_width = 4,
2965 },
2966 .p[1] = {
2967 .pre_div_shift = 3,
2968 .pre_div_width = 4,
2969 },
2970 .mux_sel_bit = 0,
2971 .freq_tbl = clk_tbl_ce5_a_clk,
2972 .clkr = {
2973 .enable_reg = 0x3d80,
2974 .enable_mask = BIT(1),
2975 .hw.init = &(struct clk_init_data){
2976 .name = "ce5_a_clk_src",
2977 .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
2978 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
2979 .ops = &clk_dyn_rcg_ops,
2980 },
2981 },
2982};
2983
2984static struct clk_branch ce5_a_clk = {
2985 .halt_reg = 0x3c20,
2986 .halt_bit = 12,
2987 .hwcg_reg = 0x3d8c,
2988 .hwcg_bit = 6,
2989 .clkr = {
2990 .enable_reg = 0x3d8c,
2991 .enable_mask = BIT(4),
2992 .hw.init = &(struct clk_init_data){
2993 .name = "ce5_a_clk",
2994 .parent_hws = (const struct clk_hw*[]){
2995 &ce5_a_clk_src.clkr.hw,
2996 },
2997 .num_parents = 1,
2998 .ops = &clk_branch_ops,
2999 .flags = CLK_SET_RATE_PARENT,
3000 },
3001 },
3002};
3003
3004static const struct freq_tbl clk_tbl_ce5_h_clk[] = {
3005 { 160000000, P_PLL0, 5, 1, 1 },
3006 { 213200000, P_PLL11, 5, 1, 1 },
3007 { }
3008};
3009
3010static struct clk_dyn_rcg ce5_h_clk_src = {
3011 .ns_reg[0] = 0x3c64,
3012 .ns_reg[1] = 0x3c68,
3013 .bank_reg = 0x3c60,
3014 .s[0] = {
3015 .src_sel_shift = 0,
3016 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
3017 },
3018 .s[1] = {
3019 .src_sel_shift = 0,
3020 .parent_map = gcc_pxo_pll8_pll0_pll14_pll18_pll11_map,
3021 },
3022 .p[0] = {
3023 .pre_div_shift = 3,
3024 .pre_div_width = 4,
3025 },
3026 .p[1] = {
3027 .pre_div_shift = 3,
3028 .pre_div_width = 4,
3029 },
3030 .mux_sel_bit = 0,
3031 .freq_tbl = clk_tbl_ce5_h_clk,
3032 .clkr = {
3033 .enable_reg = 0x3c60,
3034 .enable_mask = BIT(1),
3035 .hw.init = &(struct clk_init_data){
3036 .name = "ce5_h_clk_src",
3037 .parent_data = gcc_pxo_pll8_pll0_pll14_pll18_pll11,
3038 .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0_pll14_pll18_pll11),
3039 .ops = &clk_dyn_rcg_ops,
3040 },
3041 },
3042};
3043
3044static struct clk_branch ce5_h_clk = {
3045 .halt_reg = 0x3c20,
3046 .halt_bit = 11,
3047 .hwcg_reg = 0x3c6c,
3048 .hwcg_bit = 6,
3049 .clkr = {
3050 .enable_reg = 0x3c6c,
3051 .enable_mask = BIT(4),
3052 .hw.init = &(struct clk_init_data){
3053 .name = "ce5_h_clk",
3054 .parent_hws = (const struct clk_hw*[]){
3055 &ce5_h_clk_src.clkr.hw,
3056 },
3057 .num_parents = 1,
3058 .ops = &clk_branch_ops,
3059 .flags = CLK_SET_RATE_PARENT,
3060 },
3061 },
3062};
3063
2827static struct clk_regmap *gcc_ipq806x_clks[] = {
2828 [PLL0] = &pll0.clkr,
2829 [PLL0_VOTE] = &pll0_vote,
2830 [PLL3] = &pll3.clkr,
2831 [PLL4_VOTE] = &pll4_vote,
2832 [PLL8] = &pll8.clkr,
2833 [PLL8_VOTE] = &pll8_vote,
3064static struct clk_regmap *gcc_ipq806x_clks[] = {
3065 [PLL0] = &pll0.clkr,
3066 [PLL0_VOTE] = &pll0_vote,
3067 [PLL3] = &pll3.clkr,
3068 [PLL4_VOTE] = &pll4_vote,
3069 [PLL8] = &pll8.clkr,
3070 [PLL8_VOTE] = &pll8_vote,
3071 [PLL11] = &pll11.clkr,
2834 [PLL14] = &pll14.clkr,
2835 [PLL14_VOTE] = &pll14_vote,
2836 [PLL18] = &pll18.clkr,
2837 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
2838 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
2839 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
2840 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
2841 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,

--- 98 unchanged lines hidden (view full) ---

2940 [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
2941 [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
2942 [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
2943 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
2944 [NSSTCM_CLK] = &nss_tcm_clk.clkr,
2945 [PLL9] = &hfpll0.clkr,
2946 [PLL10] = &hfpll1.clkr,
2947 [PLL12] = &hfpll_l2.clkr,
3072 [PLL14] = &pll14.clkr,
3073 [PLL14_VOTE] = &pll14_vote,
3074 [PLL18] = &pll18.clkr,
3075 [GSBI1_UART_SRC] = &gsbi1_uart_src.clkr,
3076 [GSBI1_UART_CLK] = &gsbi1_uart_clk.clkr,
3077 [GSBI2_UART_SRC] = &gsbi2_uart_src.clkr,
3078 [GSBI2_UART_CLK] = &gsbi2_uart_clk.clkr,
3079 [GSBI4_UART_SRC] = &gsbi4_uart_src.clkr,

--- 98 unchanged lines hidden (view full) ---

3178 [GMAC_CORE4_CLK] = &gmac_core4_clk.clkr,
3179 [UBI32_CORE1_CLK_SRC] = &ubi32_core1_src_clk.clkr,
3180 [UBI32_CORE2_CLK_SRC] = &ubi32_core2_src_clk.clkr,
3181 [NSSTCM_CLK_SRC] = &nss_tcm_src.clkr,
3182 [NSSTCM_CLK] = &nss_tcm_clk.clkr,
3183 [PLL9] = &hfpll0.clkr,
3184 [PLL10] = &hfpll1.clkr,
3185 [PLL12] = &hfpll_l2.clkr,
3186 [CE5_A_CLK_SRC] = &ce5_a_clk_src.clkr,
3187 [CE5_A_CLK] = &ce5_a_clk.clkr,
3188 [CE5_H_CLK_SRC] = &ce5_h_clk_src.clkr,
3189 [CE5_H_CLK] = &ce5_h_clk.clkr,
3190 [CE5_CORE_CLK_SRC] = &ce5_core_src.clkr,
3191 [CE5_CORE_CLK] = &ce5_core_clk.clkr,
2948};
2949
2950static const struct qcom_reset_map gcc_ipq806x_resets[] = {
2951 [QDSS_STM_RESET] = { 0x2060, 6 },
2952 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
2953 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
2954 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
2955 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },

--- 242 unchanged lines hidden --- 		3192};
3193
3194static const struct qcom_reset_map gcc_ipq806x_resets[] = {
3195 [QDSS_STM_RESET] = { 0x2060, 6 },
3196 [AFAB_SMPSS_S_RESET] = { 0x20b8, 2 },
3197 [AFAB_SMPSS_M1_RESET] = { 0x20b8, 1 },
3198 [AFAB_SMPSS_M0_RESET] = { 0x20b8, 0 },
3199 [AFAB_EBI1_CH0_RESET] = { 0x20c0, 7 },

--- 242 unchanged lines hidden ---