dispcc-sc7180.c (c1ef343612cd51a8c97ca3004bffc6db33f639c6) dispcc-sc7180.c (3696ebe4e1fc45ea391412ff1a82cec9ae4f6e8f)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/platform_device.h>

--- 140 unchanged lines hidden (view full) ---

149 .cmd_rcgr = 0x22bc,
150 .mnd_width = 0,
151 .hid_width = 5,
152 .parent_map = disp_cc_parent_map_4,
153 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
154 .clkr.hw.init = &(struct clk_init_data){
155 .name = "disp_cc_mdss_ahb_clk_src",
156 .parent_data = disp_cc_parent_data_4,
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4 */
5
6#include <linux/clk-provider.h>
7#include <linux/module.h>
8#include <linux/platform_device.h>

--- 140 unchanged lines hidden (view full) ---

149 .cmd_rcgr = 0x22bc,
150 .mnd_width = 0,
151 .hid_width = 5,
152 .parent_map = disp_cc_parent_map_4,
153 .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
154 .clkr.hw.init = &(struct clk_init_data){
155 .name = "disp_cc_mdss_ahb_clk_src",
156 .parent_data = disp_cc_parent_data_4,
157 .num_parents = 2,
157 .num_parents = ARRAY_SIZE(disp_cc_parent_data_4),
158 .flags = CLK_SET_RATE_PARENT,
159 .ops = &clk_rcg2_shared_ops,
160 },
161};
162
163static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
164 .cmd_rcgr = 0x2110,
165 .mnd_width = 0,
166 .hid_width = 5,
167 .parent_map = disp_cc_parent_map_2,
168 .clkr.hw.init = &(struct clk_init_data){
169 .name = "disp_cc_mdss_byte0_clk_src",
170 .parent_data = disp_cc_parent_data_2,
158 .flags = CLK_SET_RATE_PARENT,
159 .ops = &clk_rcg2_shared_ops,
160 },
161};
162
163static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
164 .cmd_rcgr = 0x2110,
165 .mnd_width = 0,
166 .hid_width = 5,
167 .parent_map = disp_cc_parent_map_2,
168 .clkr.hw.init = &(struct clk_init_data){
169 .name = "disp_cc_mdss_byte0_clk_src",
170 .parent_data = disp_cc_parent_data_2,
171 .num_parents = 2,
171 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
172 .flags = CLK_SET_RATE_PARENT,
173 .ops = &clk_byte2_ops,
174 },
175};
176
177static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
178 F(19200000, P_BI_TCXO, 1, 0, 0),
179 { }
180};
181
182static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
183 .cmd_rcgr = 0x21dc,
184 .mnd_width = 0,
185 .hid_width = 5,
186 .parent_map = disp_cc_parent_map_0,
187 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
188 .clkr.hw.init = &(struct clk_init_data){
189 .name = "disp_cc_mdss_dp_aux_clk_src",
190 .parent_data = disp_cc_parent_data_0,
172 .flags = CLK_SET_RATE_PARENT,
173 .ops = &clk_byte2_ops,
174 },
175};
176
177static const struct freq_tbl ftbl_disp_cc_mdss_dp_aux_clk_src[] = {
178 F(19200000, P_BI_TCXO, 1, 0, 0),
179 { }
180};
181
182static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
183 .cmd_rcgr = 0x21dc,
184 .mnd_width = 0,
185 .hid_width = 5,
186 .parent_map = disp_cc_parent_map_0,
187 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
188 .clkr.hw.init = &(struct clk_init_data){
189 .name = "disp_cc_mdss_dp_aux_clk_src",
190 .parent_data = disp_cc_parent_data_0,
191 .num_parents = 2,
191 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
192 .ops = &clk_rcg2_ops,
193 },
194};
195
196static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
197 .cmd_rcgr = 0x2194,
198 .mnd_width = 0,
199 .hid_width = 5,
200 .parent_map = disp_cc_parent_map_1,
201 .clkr.hw.init = &(struct clk_init_data){
202 .name = "disp_cc_mdss_dp_crypto_clk_src",
203 .parent_data = disp_cc_parent_data_1,
192 .ops = &clk_rcg2_ops,
193 },
194};
195
196static struct clk_rcg2 disp_cc_mdss_dp_crypto_clk_src = {
197 .cmd_rcgr = 0x2194,
198 .mnd_width = 0,
199 .hid_width = 5,
200 .parent_map = disp_cc_parent_map_1,
201 .clkr.hw.init = &(struct clk_init_data){
202 .name = "disp_cc_mdss_dp_crypto_clk_src",
203 .parent_data = disp_cc_parent_data_1,
204 .num_parents = 3,
204 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
205 .flags = CLK_SET_RATE_PARENT,
206 .ops = &clk_byte2_ops,
207 },
208};
209
210static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
211 .cmd_rcgr = 0x2178,
212 .mnd_width = 0,
213 .hid_width = 5,
214 .parent_map = disp_cc_parent_map_1,
215 .clkr.hw.init = &(struct clk_init_data){
216 .name = "disp_cc_mdss_dp_link_clk_src",
217 .parent_data = disp_cc_parent_data_1,
205 .flags = CLK_SET_RATE_PARENT,
206 .ops = &clk_byte2_ops,
207 },
208};
209
210static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
211 .cmd_rcgr = 0x2178,
212 .mnd_width = 0,
213 .hid_width = 5,
214 .parent_map = disp_cc_parent_map_1,
215 .clkr.hw.init = &(struct clk_init_data){
216 .name = "disp_cc_mdss_dp_link_clk_src",
217 .parent_data = disp_cc_parent_data_1,
218 .num_parents = 3,
218 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
219 .flags = CLK_SET_RATE_PARENT,
220 .ops = &clk_byte2_ops,
221 },
222};
223
224static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
225 .cmd_rcgr = 0x21ac,
226 .mnd_width = 16,
227 .hid_width = 5,
228 .parent_map = disp_cc_parent_map_1,
229 .clkr.hw.init = &(struct clk_init_data){
230 .name = "disp_cc_mdss_dp_pixel_clk_src",
231 .parent_data = disp_cc_parent_data_1,
219 .flags = CLK_SET_RATE_PARENT,
220 .ops = &clk_byte2_ops,
221 },
222};
223
224static struct clk_rcg2 disp_cc_mdss_dp_pixel_clk_src = {
225 .cmd_rcgr = 0x21ac,
226 .mnd_width = 16,
227 .hid_width = 5,
228 .parent_map = disp_cc_parent_map_1,
229 .clkr.hw.init = &(struct clk_init_data){
230 .name = "disp_cc_mdss_dp_pixel_clk_src",
231 .parent_data = disp_cc_parent_data_1,
232 .num_parents = 3,
232 .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
233 .flags = CLK_SET_RATE_PARENT,
234 .ops = &clk_dp_ops,
235 },
236};
237
238static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
239 .cmd_rcgr = 0x2148,
240 .mnd_width = 0,
241 .hid_width = 5,
242 .parent_map = disp_cc_parent_map_2,
243 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
244 .clkr.hw.init = &(struct clk_init_data){
245 .name = "disp_cc_mdss_esc0_clk_src",
246 .parent_data = disp_cc_parent_data_2,
233 .flags = CLK_SET_RATE_PARENT,
234 .ops = &clk_dp_ops,
235 },
236};
237
238static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = {
239 .cmd_rcgr = 0x2148,
240 .mnd_width = 0,
241 .hid_width = 5,
242 .parent_map = disp_cc_parent_map_2,
243 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
244 .clkr.hw.init = &(struct clk_init_data){
245 .name = "disp_cc_mdss_esc0_clk_src",
246 .parent_data = disp_cc_parent_data_2,
247 .num_parents = 2,
247 .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
248 .ops = &clk_rcg2_ops,
249 },
250};
251
252static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
253 F(19200000, P_BI_TCXO, 1, 0, 0),
254 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
255 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),

--- 6 unchanged lines hidden (view full) ---

262 .cmd_rcgr = 0x20c8,
263 .mnd_width = 0,
264 .hid_width = 5,
265 .parent_map = disp_cc_parent_map_3,
266 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
267 .clkr.hw.init = &(struct clk_init_data){
268 .name = "disp_cc_mdss_mdp_clk_src",
269 .parent_data = disp_cc_parent_data_3,
248 .ops = &clk_rcg2_ops,
249 },
250};
251
252static const struct freq_tbl ftbl_disp_cc_mdss_mdp_clk_src[] = {
253 F(19200000, P_BI_TCXO, 1, 0, 0),
254 F(200000000, P_GPLL0_OUT_MAIN, 3, 0, 0),
255 F(300000000, P_GPLL0_OUT_MAIN, 2, 0, 0),

--- 6 unchanged lines hidden (view full) ---

262 .cmd_rcgr = 0x20c8,
263 .mnd_width = 0,
264 .hid_width = 5,
265 .parent_map = disp_cc_parent_map_3,
266 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
267 .clkr.hw.init = &(struct clk_init_data){
268 .name = "disp_cc_mdss_mdp_clk_src",
269 .parent_data = disp_cc_parent_data_3,
270 .num_parents = 4,
270 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
271 .ops = &clk_rcg2_shared_ops,
272 },
273};
274
275static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
276 .cmd_rcgr = 0x2098,
277 .mnd_width = 8,
278 .hid_width = 5,
279 .parent_map = disp_cc_parent_map_5,
280 .clkr.hw.init = &(struct clk_init_data){
281 .name = "disp_cc_mdss_pclk0_clk_src",
282 .parent_data = disp_cc_parent_data_5,
271 .ops = &clk_rcg2_shared_ops,
272 },
273};
274
275static struct clk_rcg2 disp_cc_mdss_pclk0_clk_src = {
276 .cmd_rcgr = 0x2098,
277 .mnd_width = 8,
278 .hid_width = 5,
279 .parent_map = disp_cc_parent_map_5,
280 .clkr.hw.init = &(struct clk_init_data){
281 .name = "disp_cc_mdss_pclk0_clk_src",
282 .parent_data = disp_cc_parent_data_5,
283 .num_parents = 2,
283 .num_parents = ARRAY_SIZE(disp_cc_parent_data_5),
284 .flags = CLK_SET_RATE_PARENT,
285 .ops = &clk_pixel_ops,
286 },
287};
288
289static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
290 .cmd_rcgr = 0x20e0,
291 .mnd_width = 0,
292 .hid_width = 5,
293 .parent_map = disp_cc_parent_map_3,
294 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
295 .clkr.hw.init = &(struct clk_init_data){
296 .name = "disp_cc_mdss_rot_clk_src",
297 .parent_data = disp_cc_parent_data_3,
284 .flags = CLK_SET_RATE_PARENT,
285 .ops = &clk_pixel_ops,
286 },
287};
288
289static struct clk_rcg2 disp_cc_mdss_rot_clk_src = {
290 .cmd_rcgr = 0x20e0,
291 .mnd_width = 0,
292 .hid_width = 5,
293 .parent_map = disp_cc_parent_map_3,
294 .freq_tbl = ftbl_disp_cc_mdss_mdp_clk_src,
295 .clkr.hw.init = &(struct clk_init_data){
296 .name = "disp_cc_mdss_rot_clk_src",
297 .parent_data = disp_cc_parent_data_3,
298 .num_parents = 4,
298 .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
299 .ops = &clk_rcg2_shared_ops,
300 },
301};
302
303static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
304 .cmd_rcgr = 0x20f8,
305 .mnd_width = 0,
306 .hid_width = 5,
307 .parent_map = disp_cc_parent_map_0,
308 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
309 .clkr.hw.init = &(struct clk_init_data){
310 .name = "disp_cc_mdss_vsync_clk_src",
311 .parent_data = disp_cc_parent_data_0,
299 .ops = &clk_rcg2_shared_ops,
300 },
301};
302
303static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = {
304 .cmd_rcgr = 0x20f8,
305 .mnd_width = 0,
306 .hid_width = 5,
307 .parent_map = disp_cc_parent_map_0,
308 .freq_tbl = ftbl_disp_cc_mdss_dp_aux_clk_src,
309 .clkr.hw.init = &(struct clk_init_data){
310 .name = "disp_cc_mdss_vsync_clk_src",
311 .parent_data = disp_cc_parent_data_0,
312 .num_parents = 1,
312 .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
313 .ops = &clk_rcg2_shared_ops,
314 },
315};
316
317static struct clk_branch disp_cc_mdss_ahb_clk = {
318 .halt_reg = 0x2080,
319 .halt_check = BRANCH_HALT,
320 .clkr = {

--- 441 unchanged lines hidden --- 		313 .ops = &clk_rcg2_shared_ops,
314 },
315};
316
317static struct clk_branch disp_cc_mdss_ahb_clk = {
318 .halt_reg = 0x2080,
319 .halt_check = BRANCH_HALT,
320 .clkr = {

--- 441 unchanged lines hidden ---