clk-pxa27x.c (fd13f8117f7a2d4054bf420ec1428e918a24a480) clk-pxa27x.c (3c816d950a494ae6e16b1fa017af29bc53cb7791)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Marvell PXA27x family clocks
4 *
5 * Copyright (C) 2014 Robert Jarzmik
6 *
7 * Heavily inspired from former arch/arm/mach-pxa/clock.c.
8 */
9#include <linux/clk-provider.h>
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * Marvell PXA27x family clocks
4 *
5 * Copyright (C) 2014 Robert Jarzmik
6 *
7 * Heavily inspired from former arch/arm/mach-pxa/clock.c.
8 */
9#include <linux/clk-provider.h>
10#include <mach/pxa2xx-regs.h>
11#include <linux/io.h>
12#include <linux/clk.h>
13#include <linux/clkdev.h>
14#include <linux/of.h>
15#include <linux/soc/pxa/smemc.h>
16
17#include <dt-bindings/clock/pxa-clock.h>
18#include "clk-pxa.h"
10#include <linux/io.h>
11#include <linux/clk.h>
12#include <linux/clkdev.h>
13#include <linux/of.h>
14#include <linux/soc/pxa/smemc.h>
15
16#include <dt-bindings/clock/pxa-clock.h>
17#include "clk-pxa.h"
18#include "clk-pxa2xx.h"
19
20#define KHz 1000
21#define MHz (1000 * 1000)
22
23enum {
24 PXA_CORE_13Mhz = 0,
25 PXA_CORE_RUN,
26 PXA_CORE_TURBO,

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47 ((B) ? CLKCFG_FASTBUS : 0) | \
48 ((HT) ? CLKCFG_HALFTURBO : 0) | \
49 ((T) ? CLKCFG_TURBO : 0))
50#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
51
52/* Define the refresh period in mSec for the SDRAM and the number of rows */
53#define SDRAM_TREF 64 /* standard 64ms SDRAM */
54
19
20#define KHz 1000
21#define MHz (1000 * 1000)
22
23enum {
24 PXA_CORE_13Mhz = 0,
25 PXA_CORE_RUN,
26 PXA_CORE_TURBO,

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47 ((B) ? CLKCFG_FASTBUS : 0) | \
48 ((HT) ? CLKCFG_HALFTURBO : 0) | \
49 ((T) ? CLKCFG_TURBO : 0))
50#define PXA27x_CCCR(A, L, N2) (A << 25 | N2 << 7 | L)
51
52/* Define the refresh period in mSec for the SDRAM and the number of rows */
53#define SDRAM_TREF 64 /* standard 64ms SDRAM */
54
55static void __iomem *clk_regs;
56
55static const char * const get_freq_khz[] = {
56 "core", "run", "cpll", "memory",
57 "system_bus"
58};
59
60static u32 mdrefr_dri(unsigned int freq_khz)
61{
62 u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();

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94 pr_info("System bus clock: %ld.%02ldMHz\n",
95 clks[4] / 1000000, (clks[4] % 1000000) / 10000);
96 }
97 return (unsigned int)clks[0] / KHz;
98}
99
100bool pxa27x_is_ppll_disabled(void)
101{
57static const char * const get_freq_khz[] = {
58 "core", "run", "cpll", "memory",
59 "system_bus"
60};
61
62static u32 mdrefr_dri(unsigned int freq_khz)
63{
64 u32 interval = freq_khz * SDRAM_TREF / pxa2xx_smemc_get_sdram_rows();

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96 pr_info("System bus clock: %ld.%02ldMHz\n",
97 clks[4] / 1000000, (clks[4] % 1000000) / 10000);
98 }
99 return (unsigned int)clks[0] / KHz;
100}
101
102bool pxa27x_is_ppll_disabled(void)
103{
102 unsigned long ccsr = readl(CCSR);
104 unsigned long ccsr = readl(clk_regs + CCSR);
103
104 return ccsr & (1 << CCCR_PPDIS_BIT);
105}
106
107#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
108 bit, is_lp, flags) \
109 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
110 is_lp, CKEN, CKEN_ ## bit, flags)

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196};
197
198static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
199 unsigned long parent_rate)
200{
201 unsigned long clkcfg;
202 unsigned int t, ht;
203 unsigned int l, L, n2, N;
105
106 return ccsr & (1 << CCCR_PPDIS_BIT);
107}
108
109#define PXA27X_CKEN(dev_id, con_id, parents, mult_hp, div_hp, \
110 bit, is_lp, flags) \
111 PXA_CKEN(dev_id, con_id, bit, parents, 1, 1, mult_hp, div_hp, \
112 is_lp, CKEN, CKEN_ ## bit, flags)

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198};
199
200static unsigned long clk_pxa27x_cpll_get_rate(struct clk_hw *hw,
201 unsigned long parent_rate)
202{
203 unsigned long clkcfg;
204 unsigned int t, ht;
205 unsigned int l, L, n2, N;
204 unsigned long ccsr = readl(CCSR);
206 unsigned long ccsr = readl(clk_regs + CCSR);
205
206 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
207 t = clkcfg & (1 << 0);
208 ht = clkcfg & (1 << 2);
209
210 l = ccsr & CCSR_L_MASK;
211 n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
212 L = l * parent_rate;

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230 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
231 for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
232 if (pxa27x_freqs[i].cpll == rate)
233 break;
234
235 if (i >= ARRAY_SIZE(pxa27x_freqs))
236 return -EINVAL;
237
207
208 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
209 t = clkcfg & (1 << 0);
210 ht = clkcfg & (1 << 2);
211
212 l = ccsr & CCSR_L_MASK;
213 n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
214 L = l * parent_rate;

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232 pr_debug("%s(rate=%lu parent_rate=%lu)\n", __func__, rate, parent_rate);
233 for (i = 0; i < ARRAY_SIZE(pxa27x_freqs); i++)
234 if (pxa27x_freqs[i].cpll == rate)
235 break;
236
237 if (i >= ARRAY_SIZE(pxa27x_freqs))
238 return -EINVAL;
239
238 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, CCCR);
240 pxa2xx_cpll_change(&pxa27x_freqs[i], mdrefr_dri, clk_regs + CCCR);
239 return 0;
240}
241
242PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
243RATE_OPS(clk_pxa27x_cpll, "cpll");
244
245static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
246 unsigned long parent_rate)
247{
248 unsigned int l, osc_forced;
241 return 0;
242}
243
244PARENTS(clk_pxa27x_cpll) = { "osc_13mhz" };
245RATE_OPS(clk_pxa27x_cpll, "cpll");
246
247static unsigned long clk_pxa27x_lcd_base_get_rate(struct clk_hw *hw,
248 unsigned long parent_rate)
249{
250 unsigned int l, osc_forced;
249 unsigned long ccsr = readl(CCSR);
250 unsigned long cccr = readl(CCCR);
251 unsigned long ccsr = readl(clk_regs + CCSR);
252 unsigned long cccr = readl(clk_regs + CCCR);
251
252 l = ccsr & CCSR_L_MASK;
253 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
254 if (osc_forced) {
255 if (cccr & (1 << CCCR_LCD_26_BIT))
256 return parent_rate * 2;
257 else
258 return parent_rate;

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263 if (l <= 16)
264 return parent_rate / 2;
265 return parent_rate / 4;
266}
267
268static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
269{
270 unsigned int osc_forced;
253
254 l = ccsr & CCSR_L_MASK;
255 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
256 if (osc_forced) {
257 if (cccr & (1 << CCCR_LCD_26_BIT))
258 return parent_rate * 2;
259 else
260 return parent_rate;

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265 if (l <= 16)
266 return parent_rate / 2;
267 return parent_rate / 4;
268}
269
270static u8 clk_pxa27x_lcd_base_get_parent(struct clk_hw *hw)
271{
272 unsigned int osc_forced;
271 unsigned long ccsr = readl(CCSR);
273 unsigned long ccsr = readl(clk_regs + CCSR);
272
273 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
274 if (osc_forced)
275 return PXA_LCD_13Mhz;
276 else
277 return PXA_LCD_RUN;
278}
279

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292 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
293 clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
294}
295
296static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
297{
298 unsigned long clkcfg;
299 unsigned int t, ht, osc_forced;
274
275 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
276 if (osc_forced)
277 return PXA_LCD_13Mhz;
278 else
279 return PXA_LCD_RUN;
280}
281

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294 clk_register_fixed_rate(NULL, "clk_dummy", NULL, 0, 0);
295 clk_register_fixed_factor(NULL, "ppll_312mhz", "osc_13mhz", 0, 24, 1);
296}
297
298static u8 clk_pxa27x_core_get_parent(struct clk_hw *hw)
299{
300 unsigned long clkcfg;
301 unsigned int t, ht, osc_forced;
300 unsigned long ccsr = readl(CCSR);
302 unsigned long ccsr = readl(clk_regs + CCSR);
301
302 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
303 if (osc_forced)
304 return PXA_CORE_13Mhz;
305
306 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
307 t = clkcfg & (1 << 0);
308 ht = clkcfg & (1 << 2);

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329}
330
331PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
332MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
333
334static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
335 unsigned long parent_rate)
336{
303
304 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
305 if (osc_forced)
306 return PXA_CORE_13Mhz;
307
308 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
309 t = clkcfg & (1 << 0);
310 ht = clkcfg & (1 << 2);

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331}
332
333PARENTS(clk_pxa27x_core) = { "osc_13mhz", "run", "cpll" };
334MUX_OPS(clk_pxa27x_core, "core", CLK_SET_RATE_PARENT);
335
336static unsigned long clk_pxa27x_run_get_rate(struct clk_hw *hw,
337 unsigned long parent_rate)
338{
337 unsigned long ccsr = readl(CCSR);
339 unsigned long ccsr = readl(clk_regs + CCSR);
338 unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
339
340 return (parent_rate / n2) * 2;
341}
342PARENTS(clk_pxa27x_run) = { "cpll" };
343RATE_RO_OPS(clk_pxa27x_run, "run");
344
345static void __init pxa27x_register_core(void)

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352 clk_register_clk_pxa27x_core());
353}
354
355static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
356 unsigned long parent_rate)
357{
358 unsigned long clkcfg;
359 unsigned int b, osc_forced;
340 unsigned int n2 = (ccsr & CCSR_N2_MASK) >> CCSR_N2_SHIFT;
341
342 return (parent_rate / n2) * 2;
343}
344PARENTS(clk_pxa27x_run) = { "cpll" };
345RATE_RO_OPS(clk_pxa27x_run, "run");
346
347static void __init pxa27x_register_core(void)

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354 clk_register_clk_pxa27x_core());
355}
356
357static unsigned long clk_pxa27x_system_bus_get_rate(struct clk_hw *hw,
358 unsigned long parent_rate)
359{
360 unsigned long clkcfg;
361 unsigned int b, osc_forced;
360 unsigned long ccsr = readl(CCSR);
362 unsigned long ccsr = readl(clk_regs + CCSR);
361
362 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
363 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
364 b = clkcfg & (1 << 3);
365
366 if (osc_forced)
367 return parent_rate;
368 if (b)
369 return parent_rate;
370 else
371 return parent_rate / 2;
372}
373
374static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
375{
376 unsigned int osc_forced;
363
364 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
365 asm("mrc\tp14, 0, %0, c6, c0, 0" : "=r" (clkcfg));
366 b = clkcfg & (1 << 3);
367
368 if (osc_forced)
369 return parent_rate;
370 if (b)
371 return parent_rate;
372 else
373 return parent_rate / 2;
374}
375
376static u8 clk_pxa27x_system_bus_get_parent(struct clk_hw *hw)
377{
378 unsigned int osc_forced;
377 unsigned long ccsr = readl(CCSR);
379 unsigned long ccsr = readl(clk_regs + CCSR);
378
379 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
380 if (osc_forced)
381 return PXA_BUS_13Mhz;
382 else
383 return PXA_BUS_RUN;
384}
385
386PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
387MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
388
389static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
390 unsigned long parent_rate)
391{
392 unsigned int a, l, osc_forced;
380
381 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
382 if (osc_forced)
383 return PXA_BUS_13Mhz;
384 else
385 return PXA_BUS_RUN;
386}
387
388PARENTS(clk_pxa27x_system_bus) = { "osc_13mhz", "run" };
389MUX_RO_RATE_RO_OPS(clk_pxa27x_system_bus, "system_bus");
390
391static unsigned long clk_pxa27x_memory_get_rate(struct clk_hw *hw,
392 unsigned long parent_rate)
393{
394 unsigned int a, l, osc_forced;
393 unsigned long cccr = readl(CCCR);
394 unsigned long ccsr = readl(CCSR);
395 unsigned long cccr = readl(clk_regs + CCCR);
396 unsigned long ccsr = readl(clk_regs + CCSR);
395
396 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
397 a = cccr & (1 << CCCR_A_BIT);
398 l = ccsr & CCSR_L_MASK;
399
400 if (osc_forced || a)
401 return parent_rate;
402 if (l <= 10)
403 return parent_rate;
404 if (l <= 20)
405 return parent_rate / 2;
406 return parent_rate / 4;
407}
408
409static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
410{
411 unsigned int osc_forced, a;
397
398 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
399 a = cccr & (1 << CCCR_A_BIT);
400 l = ccsr & CCSR_L_MASK;
401
402 if (osc_forced || a)
403 return parent_rate;
404 if (l <= 10)
405 return parent_rate;
406 if (l <= 20)
407 return parent_rate / 2;
408 return parent_rate / 4;
409}
410
411static u8 clk_pxa27x_memory_get_parent(struct clk_hw *hw)
412{
413 unsigned int osc_forced, a;
412 unsigned long cccr = readl(CCCR);
413 unsigned long ccsr = readl(CCSR);
414 unsigned long cccr = readl(clk_regs + CCCR);
415 unsigned long ccsr = readl(clk_regs + CCSR);
414
415 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
416 a = cccr & (1 << CCCR_A_BIT);
417 if (osc_forced)
418 return PXA_MEM_13Mhz;
419 if (a)
420 return PXA_MEM_SYSTEM_BUS;
421 else

--- 38 unchanged lines hidden (view full) ---

460 pxa27x_register_core();
461 clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
462 clk_register_clk_pxa27x_system_bus());
463 clkdev_pxa_register(CLK_NONE, "memory", NULL,
464 clk_register_clk_pxa27x_memory());
465 clk_register_clk_pxa27x_lcd_base();
466}
467
416
417 osc_forced = ccsr & (1 << CCCR_CPDIS_BIT);
418 a = cccr & (1 << CCCR_A_BIT);
419 if (osc_forced)
420 return PXA_MEM_13Mhz;
421 if (a)
422 return PXA_MEM_SYSTEM_BUS;
423 else

--- 38 unchanged lines hidden (view full) ---

462 pxa27x_register_core();
463 clkdev_pxa_register(CLK_NONE, "system_bus", NULL,
464 clk_register_clk_pxa27x_system_bus());
465 clkdev_pxa_register(CLK_NONE, "memory", NULL,
466 clk_register_clk_pxa27x_memory());
467 clk_register_clk_pxa27x_lcd_base();
468}
469
468int __init pxa27x_clocks_init(void)
470int __init pxa27x_clocks_init(void __iomem *regs)
469{
471{
472 clk_regs = regs;
470 pxa27x_base_clocks_init();
471 pxa27x_dummy_clocks_init();
473 pxa27x_base_clocks_init();
474 pxa27x_dummy_clocks_init();
472 return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks));
475 return clk_pxa_cken_init(pxa27x_clocks, ARRAY_SIZE(pxa27x_clocks), regs);
473}
474
475static void __init pxa27x_dt_clocks_init(struct device_node *np)
476{
476}
477
478static void __init pxa27x_dt_clocks_init(struct device_node *np)
479{
477 pxa27x_clocks_init();
480 pxa27x_clocks_init(ioremap(0x41300000ul, 0x10));
478 clk_pxa_dt_common_init(np);
479}
480CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);
481 clk_pxa_dt_common_init(np);
482}
483CLK_OF_DECLARE(pxa_clks, "marvell,pxa270-clocks", pxa27x_dt_clocks_init);