jz4740-cgu.c (ff1930c6bdf031e72e101a8aa47d54e73a745f93) jz4740-cgu.c (41dd641e9a1a7229383f9b342a57cb6720e7ea46)
1/*
2 * Ingenic JZ4740 SoC CGU driver
3 *
4 * Copyright (c) 2015 Imagination Technologies
5 * Author: Paul Burton <paul.burton@imgtec.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/delay.h>
20#include <linux/of.h>
21#include <dt-bindings/clock/jz4740-cgu.h>
1/*
2 * Ingenic JZ4740 SoC CGU driver
3 *
4 * Copyright (c) 2015 Imagination Technologies
5 * Author: Paul Burton <paul.burton@imgtec.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

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14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 */
17
18#include <linux/clk-provider.h>
19#include <linux/delay.h>
20#include <linux/of.h>
21#include <dt-bindings/clock/jz4740-cgu.h>
22#include <asm/mach-jz4740/clock.h>
22#include "cgu.h"
23
24/* CGU register offsets */
25#define CGU_REG_CPCCR 0x00
23#include "cgu.h"
24
25/* CGU register offsets */
26#define CGU_REG_CPCCR 0x00
27#define CGU_REG_LCR 0x04
26#define CGU_REG_CPPCR 0x10
27#define CGU_REG_SCR 0x24
28#define CGU_REG_I2SCDR 0x60
29#define CGU_REG_LPCDR 0x64
30#define CGU_REG_MSCCDR 0x68
31#define CGU_REG_UHCCDR 0x6c
32#define CGU_REG_SSICDR 0x74
33
34/* bits within a PLL control register */
35#define PLLCTL_M_SHIFT 23
36#define PLLCTL_M_MASK (0x1ff << PLLCTL_M_SHIFT)
37#define PLLCTL_N_SHIFT 18
38#define PLLCTL_N_MASK (0x1f << PLLCTL_N_SHIFT)
39#define PLLCTL_OD_SHIFT 16
40#define PLLCTL_OD_MASK (0x3 << PLLCTL_OD_SHIFT)
41#define PLLCTL_STABLE (1 << 10)
42#define PLLCTL_BYPASS (1 << 9)
43#define PLLCTL_ENABLE (1 << 8)
44
28#define CGU_REG_CPPCR 0x10
29#define CGU_REG_SCR 0x24
30#define CGU_REG_I2SCDR 0x60
31#define CGU_REG_LPCDR 0x64
32#define CGU_REG_MSCCDR 0x68
33#define CGU_REG_UHCCDR 0x6c
34#define CGU_REG_SSICDR 0x74
35
36/* bits within a PLL control register */
37#define PLLCTL_M_SHIFT 23
38#define PLLCTL_M_MASK (0x1ff << PLLCTL_M_SHIFT)
39#define PLLCTL_N_SHIFT 18
40#define PLLCTL_N_MASK (0x1f << PLLCTL_N_SHIFT)
41#define PLLCTL_OD_SHIFT 16
42#define PLLCTL_OD_MASK (0x3 << PLLCTL_OD_SHIFT)
43#define PLLCTL_STABLE (1 << 10)
44#define PLLCTL_BYPASS (1 << 9)
45#define PLLCTL_ENABLE (1 << 8)
46
47/* bits within the LCR register */
48#define LCR_SLEEP (1 << 0)
49
45static struct ingenic_cgu *cgu;
46
47static const s8 pll_od_encoding[4] = {
48 0x0, 0x1, -1, 0x3,
49};
50
51static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
52

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215 return;
216 }
217
218 retval = ingenic_cgu_register_clocks(cgu);
219 if (retval)
220 pr_err("%s: failed to register CGU Clocks\n", __func__);
221}
222CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
50static struct ingenic_cgu *cgu;
51
52static const s8 pll_od_encoding[4] = {
53 0x0, 0x1, -1, 0x3,
54};
55
56static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
57

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220 return;
221 }
222
223 retval = ingenic_cgu_register_clocks(cgu);
224 if (retval)
225 pr_err("%s: failed to register CGU Clocks\n", __func__);
226}
227CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
228
229void jz4740_clock_set_wait_mode(enum jz4740_wait_mode mode)
230{
231 uint32_t lcr = readl(cgu->base + CGU_REG_LCR);
232
233 switch (mode) {
234 case JZ4740_WAIT_MODE_IDLE:
235 lcr &= ~LCR_SLEEP;
236 break;
237
238 case JZ4740_WAIT_MODE_SLEEP:
239 lcr |= LCR_SLEEP;
240 break;
241 }
242
243 writel(lcr, cgu->base + CGU_REG_LCR);
244}