jz4740-cgu.c (cbd32a1c56e36fedaa93a727699188bd3e6e6f67) jz4740-cgu.c (03d570e1a4dc669457af2888999ecc9548fc0d2a)
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Ingenic JZ4740 SoC CGU driver
4 *
5 * Copyright (c) 2015 Imagination Technologies
6 * Author: Paul Burton <paul.burton@mips.com>
7 */
8

--- 39 unchanged lines hidden (view full) ---

48static const s8 pll_od_encoding[4] = {
49 0x0, 0x1, -1, 0x3,
50};
51
52static const u8 jz4740_cgu_cpccr_div_table[] = {
53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
54};
55
1// SPDX-License-Identifier: GPL-2.0-or-later
2/*
3 * Ingenic JZ4740 SoC CGU driver
4 *
5 * Copyright (c) 2015 Imagination Technologies
6 * Author: Paul Burton <paul.burton@mips.com>
7 */
8

--- 39 unchanged lines hidden (view full) ---

48static const s8 pll_od_encoding[4] = {
49 0x0, 0x1, -1, 0x3,
50};
51
52static const u8 jz4740_cgu_cpccr_div_table[] = {
53 1, 2, 3, 4, 6, 8, 12, 16, 24, 32,
54};
55
56static const u8 jz4740_cgu_pll_half_div_table[] = {
57 2, 1,
58};
59
56static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
57
58 /* External clocks */
59
60 [JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT },
61 [JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
62
63 [JZ4740_CLK_PLL] = {

--- 17 unchanged lines hidden (view full) ---

81 },
82 },
83
84 /* Muxes & dividers */
85
86 [JZ4740_CLK_PLL_HALF] = {
87 "pll half", CGU_CLK_DIV,
88 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
60static const struct ingenic_cgu_clk_info jz4740_cgu_clocks[] = {
61
62 /* External clocks */
63
64 [JZ4740_CLK_EXT] = { "ext", CGU_CLK_EXT },
65 [JZ4740_CLK_RTC] = { "rtc", CGU_CLK_EXT },
66
67 [JZ4740_CLK_PLL] = {

--- 17 unchanged lines hidden (view full) ---

85 },
86 },
87
88 /* Muxes & dividers */
89
90 [JZ4740_CLK_PLL_HALF] = {
91 "pll half", CGU_CLK_DIV,
92 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
89 .div = { CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1 },
93 .div = {
94 CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1,
95 jz4740_cgu_pll_half_div_table,
96 },
90 },
91
92 [JZ4740_CLK_CCLK] = {
93 "cclk", CGU_CLK_DIV,
94 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
95 .div = {
96 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
97 jz4740_cgu_cpccr_div_table,

--- 138 unchanged lines hidden (view full) ---

236 }
237
238 retval = ingenic_cgu_register_clocks(cgu);
239 if (retval)
240 pr_err("%s: failed to register CGU Clocks\n", __func__);
241
242 ingenic_cgu_register_syscore_ops(cgu);
243}
97 },
98
99 [JZ4740_CLK_CCLK] = {
100 "cclk", CGU_CLK_DIV,
101 .parents = { JZ4740_CLK_PLL, -1, -1, -1 },
102 .div = {
103 CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1,
104 jz4740_cgu_cpccr_div_table,

--- 138 unchanged lines hidden (view full) ---

243 }
244
245 retval = ingenic_cgu_register_clocks(cgu);
246 if (retval)
247 pr_err("%s: failed to register CGU Clocks\n", __func__);
248
249 ingenic_cgu_register_syscore_ops(cgu);
250}
244CLK_OF_DECLARE(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);
251CLK_OF_DECLARE_DRIVER(jz4740_cgu, "ingenic,jz4740-cgu", jz4740_cgu_init);