| clk.c (762f99f4f3cb41a775b5157dd761217beba65873) | clk.c (08edf70457b375d2f09aaee5ba07777046293d93) |
|---|---|
| 1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Hisilicon clock driver 4 * 5 * Copyright (c) 2012-2013 Hisilicon Limited. 6 * Copyright (c) 2012-2013 Linaro Limited. 7 * 8 * Author: Haojian Zhuang <haojian.zhuang@linaro.org> --- 148 unchanged lines hidden (view full) --- 157 for (i = 0; i < nums; i++) { 158 u32 mask = BIT(clks[i].width) - 1; 159 160 clk = clk_register_mux_table(NULL, clks[i].name, 161 clks[i].parent_names, 162 clks[i].num_parents, clks[i].flags, 163 base + clks[i].offset, clks[i].shift, 164 mask, clks[i].mux_flags, | 1// SPDX-License-Identifier: GPL-2.0-or-later 2/* 3 * Hisilicon clock driver 4 * 5 * Copyright (c) 2012-2013 Hisilicon Limited. 6 * Copyright (c) 2012-2013 Linaro Limited. 7 * 8 * Author: Haojian Zhuang <haojian.zhuang@linaro.org> --- 148 unchanged lines hidden (view full) --- 157 for (i = 0; i < nums; i++) { 158 u32 mask = BIT(clks[i].width) - 1; 159 160 clk = clk_register_mux_table(NULL, clks[i].name, 161 clks[i].parent_names, 162 clks[i].num_parents, clks[i].flags, 163 base + clks[i].offset, clks[i].shift, 164 mask, clks[i].mux_flags, |
| 165 (u32 *)clks[i].table, &hisi_clk_lock); | 165 clks[i].table, &hisi_clk_lock); |
| 166 if (IS_ERR(clk)) { 167 pr_err("%s: failed to register clock %s\n", 168 __func__, clks[i].name); 169 goto err; 170 } 171 172 if (clks[i].alias) 173 clk_register_clkdev(clk, clks[i].alias, NULL); --- 170 unchanged lines hidden --- | 166 if (IS_ERR(clk)) { 167 pr_err("%s: failed to register clock %s\n", 168 __func__, clks[i].name); 169 goto err; 170 } 171 172 if (clks[i].alias) 173 clk_register_clkdev(clk, clks[i].alias, NULL); --- 170 unchanged lines hidden --- |