clk.c (16d1c8991cd6f25083ec43c15bed7ae30fbbe41e) clk.c (75af25f581b1ffc63e06cb01547b3141d4cd5f58)
1/*
2 * Hisilicon clock driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>

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32#include <linux/of_address.h>
33#include <linux/of_device.h>
34#include <linux/slab.h>
35#include <linux/clk.h>
36
37#include "clk.h"
38
39static DEFINE_SPINLOCK(hisi_clk_lock);
1/*
2 * Hisilicon clock driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>

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32#include <linux/of_address.h>
33#include <linux/of_device.h>
34#include <linux/slab.h>
35#include <linux/clk.h>
36
37#include "clk.h"
38
39static DEFINE_SPINLOCK(hisi_clk_lock);
40static struct clk **clk_table;
41static struct clk_onecell_data clk_data;
42
40
43void __init hisi_clk_init(struct device_node *np, int nr_clks)
41struct hisi_clock_data __init *hisi_clk_init(struct device_node *np,
42 int nr_clks)
44{
43{
44 struct hisi_clock_data *clk_data;
45 struct clk **clk_table;
46 void __iomem *base;
47
48 if (np) {
49 base = of_iomap(np, 0);
50 if (!base) {
51 pr_err("failed to map Hisilicon clock registers\n");
52 goto err;
53 }
54 } else {
55 pr_err("failed to find Hisilicon clock node in DTS\n");
56 goto err;
57 }
58
59 clk_data = kzalloc(sizeof(*clk_data), GFP_KERNEL);
60 if (!clk_data) {
61 pr_err("%s: could not allocate clock data\n", __func__);
62 goto err;
63 }
64 clk_data->base = base;
65
45 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
46 if (!clk_table) {
47 pr_err("%s: could not allocate clock lookup table\n", __func__);
66 clk_table = kzalloc(sizeof(struct clk *) * nr_clks, GFP_KERNEL);
67 if (!clk_table) {
68 pr_err("%s: could not allocate clock lookup table\n", __func__);
48 return;
69 goto err_data;
49 }
70 }
50 clk_data.clks = clk_table;
51 clk_data.clk_num = nr_clks;
52 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
71 clk_data->clk_data.clks = clk_table;
72 clk_data->clk_data.clk_num = nr_clks;
73 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data->clk_data);
74 return clk_data;
75err_data:
76 kfree(clk_data);
77err:
78 return NULL;
53}
54
55void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
79}
80
81void __init hisi_clk_register_fixed_rate(struct hisi_fixed_rate_clock *clks,
56 int nums, void __iomem *base)
82 int nums, struct hisi_clock_data *data)
57{
58 struct clk *clk;
59 int i;
60
61 for (i = 0; i < nums; i++) {
62 clk = clk_register_fixed_rate(NULL, clks[i].name,
63 clks[i].parent_name,
64 clks[i].flags,
65 clks[i].fixed_rate);
66 if (IS_ERR(clk)) {
67 pr_err("%s: failed to register clock %s\n",
68 __func__, clks[i].name);
69 continue;
70 }
83{
84 struct clk *clk;
85 int i;
86
87 for (i = 0; i < nums; i++) {
88 clk = clk_register_fixed_rate(NULL, clks[i].name,
89 clks[i].parent_name,
90 clks[i].flags,
91 clks[i].fixed_rate);
92 if (IS_ERR(clk)) {
93 pr_err("%s: failed to register clock %s\n",
94 __func__, clks[i].name);
95 continue;
96 }
71 clk_table[clks[i].id] = clk;
97 data->clk_data.clks[clks[i].id] = clk;
72 }
73}
74
75void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
98 }
99}
100
101void __init hisi_clk_register_fixed_factor(struct hisi_fixed_factor_clock *clks,
76 int nums, void __iomem *base)
102 int nums,
103 struct hisi_clock_data *data)
77{
78 struct clk *clk;
79 int i;
80
81 for (i = 0; i < nums; i++) {
82 clk = clk_register_fixed_factor(NULL, clks[i].name,
83 clks[i].parent_name,
84 clks[i].flags, clks[i].mult,
85 clks[i].div);
86 if (IS_ERR(clk)) {
87 pr_err("%s: failed to register clock %s\n",
88 __func__, clks[i].name);
89 continue;
90 }
104{
105 struct clk *clk;
106 int i;
107
108 for (i = 0; i < nums; i++) {
109 clk = clk_register_fixed_factor(NULL, clks[i].name,
110 clks[i].parent_name,
111 clks[i].flags, clks[i].mult,
112 clks[i].div);
113 if (IS_ERR(clk)) {
114 pr_err("%s: failed to register clock %s\n",
115 __func__, clks[i].name);
116 continue;
117 }
91 clk_table[clks[i].id] = clk;
118 data->clk_data.clks[clks[i].id] = clk;
92 }
93}
94
95void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
119 }
120}
121
122void __init hisi_clk_register_mux(struct hisi_mux_clock *clks,
96 int nums, void __iomem *base)
123 int nums, struct hisi_clock_data *data)
97{
98 struct clk *clk;
124{
125 struct clk *clk;
126 void __iomem *base = data->base;
99 int i;
100
101 for (i = 0; i < nums; i++) {
102 clk = clk_register_mux(NULL, clks[i].name, clks[i].parent_names,
103 clks[i].num_parents, clks[i].flags,
104 base + clks[i].offset, clks[i].shift,
105 clks[i].width, clks[i].mux_flags,
106 &hisi_clk_lock);
107 if (IS_ERR(clk)) {
108 pr_err("%s: failed to register clock %s\n",
109 __func__, clks[i].name);
110 continue;
111 }
112
113 if (clks[i].alias)
114 clk_register_clkdev(clk, clks[i].alias, NULL);
115
127 int i;
128
129 for (i = 0; i < nums; i++) {
130 clk = clk_register_mux(NULL, clks[i].name, clks[i].parent_names,
131 clks[i].num_parents, clks[i].flags,
132 base + clks[i].offset, clks[i].shift,
133 clks[i].width, clks[i].mux_flags,
134 &hisi_clk_lock);
135 if (IS_ERR(clk)) {
136 pr_err("%s: failed to register clock %s\n",
137 __func__, clks[i].name);
138 continue;
139 }
140
141 if (clks[i].alias)
142 clk_register_clkdev(clk, clks[i].alias, NULL);
143
116 clk_table[clks[i].id] = clk;
144 data->clk_data.clks[clks[i].id] = clk;
117 }
118}
119
120void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
145 }
146}
147
148void __init hisi_clk_register_divider(struct hisi_divider_clock *clks,
121 int nums, void __iomem *base)
149 int nums, struct hisi_clock_data *data)
122{
123 struct clk *clk;
150{
151 struct clk *clk;
152 void __iomem *base = data->base;
124 int i;
125
126 for (i = 0; i < nums; i++) {
127 clk = clk_register_divider_table(NULL, clks[i].name,
128 clks[i].parent_name,
129 clks[i].flags,
130 base + clks[i].offset,
131 clks[i].shift, clks[i].width,

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136 pr_err("%s: failed to register clock %s\n",
137 __func__, clks[i].name);
138 continue;
139 }
140
141 if (clks[i].alias)
142 clk_register_clkdev(clk, clks[i].alias, NULL);
143
153 int i;
154
155 for (i = 0; i < nums; i++) {
156 clk = clk_register_divider_table(NULL, clks[i].name,
157 clks[i].parent_name,
158 clks[i].flags,
159 base + clks[i].offset,
160 clks[i].shift, clks[i].width,

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165 pr_err("%s: failed to register clock %s\n",
166 __func__, clks[i].name);
167 continue;
168 }
169
170 if (clks[i].alias)
171 clk_register_clkdev(clk, clks[i].alias, NULL);
172
144 clk_table[clks[i].id] = clk;
173 data->clk_data.clks[clks[i].id] = clk;
145 }
146}
147
148void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
174 }
175}
176
177void __init hisi_clk_register_gate_sep(struct hisi_gate_clock *clks,
149 int nums, void __iomem *base)
178 int nums, struct hisi_clock_data *data)
150{
151 struct clk *clk;
179{
180 struct clk *clk;
181 void __iomem *base = data->base;
152 int i;
153
154 for (i = 0; i < nums; i++) {
155 clk = hisi_register_clkgate_sep(NULL, clks[i].name,
156 clks[i].parent_name,
157 clks[i].flags,
158 base + clks[i].offset,
159 clks[i].bit_idx,
160 clks[i].gate_flags,
161 &hisi_clk_lock);
162 if (IS_ERR(clk)) {
163 pr_err("%s: failed to register clock %s\n",
164 __func__, clks[i].name);
165 continue;
166 }
167
168 if (clks[i].alias)
169 clk_register_clkdev(clk, clks[i].alias, NULL);
170
182 int i;
183
184 for (i = 0; i < nums; i++) {
185 clk = hisi_register_clkgate_sep(NULL, clks[i].name,
186 clks[i].parent_name,
187 clks[i].flags,
188 base + clks[i].offset,
189 clks[i].bit_idx,
190 clks[i].gate_flags,
191 &hisi_clk_lock);
192 if (IS_ERR(clk)) {
193 pr_err("%s: failed to register clock %s\n",
194 __func__, clks[i].name);
195 continue;
196 }
197
198 if (clks[i].alias)
199 clk_register_clkdev(clk, clks[i].alias, NULL);
200
171 clk_table[clks[i].id] = clk;
201 data->clk_data.clks[clks[i].id] = clk;
172 }
173}
202 }
203}