clk-hip04.c (d3e6573c48f4472147b37e92cb345271e04d34d9) clk-hip04.c (75af25f581b1ffc63e06cb01547b3141d4cd5f58)
1/*
2 * Hisilicon HiP04 clock driver
3 *
4 * Copyright (c) 2013-2014 Hisilicon Limited.
5 * Copyright (c) 2013-2014 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *

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40static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
41 { HIP04_OSC50M, "osc50m", NULL, CLK_IS_ROOT, 50000000, },
42 { HIP04_CLK_50M, "clk50m", NULL, CLK_IS_ROOT, 50000000, },
43 { HIP04_CLK_168M, "clk168m", NULL, CLK_IS_ROOT, 168750000, },
44};
45
46static void __init hip04_clk_init(struct device_node *np)
47{
1/*
2 * Hisilicon HiP04 clock driver
3 *
4 * Copyright (c) 2013-2014 Hisilicon Limited.
5 * Copyright (c) 2013-2014 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 *

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40static struct hisi_fixed_rate_clock hip04_fixed_rate_clks[] __initdata = {
41 { HIP04_OSC50M, "osc50m", NULL, CLK_IS_ROOT, 50000000, },
42 { HIP04_CLK_50M, "clk50m", NULL, CLK_IS_ROOT, 50000000, },
43 { HIP04_CLK_168M, "clk168m", NULL, CLK_IS_ROOT, 168750000, },
44};
45
46static void __init hip04_clk_init(struct device_node *np)
47{
48 hisi_clk_init(np, HIP04_NR_CLKS);
48 struct hisi_clock_data *clk_data;
49
49
50 clk_data = hisi_clk_init(np, HIP04_NR_CLKS);
51 if (!clk_data)
52 return;
53
50 hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
51 ARRAY_SIZE(hip04_fixed_rate_clks),
54 hisi_clk_register_fixed_rate(hip04_fixed_rate_clks,
55 ARRAY_SIZE(hip04_fixed_rate_clks),
52 NULL);
56 clk_data);
53}
54CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);
57}
58CLK_OF_DECLARE(hip04_clk, "hisilicon,hip04-clock", hip04_clk_init);