clk-hi3620.c (e19b9137142988bec5a76c5f8bdf12a77ea802b0) clk-hi3620.c (75af25f581b1ffc63e06cb01547b3141d4cd5f58)
1/*
2 * Hisilicon Hi3620 clock driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>

--- 196 unchanged lines hidden (view full) ---

205 { HI3620_MMC_CLK1, "mmc_clk1", "mmc1_mux2", CLK_SET_RATE_PARENT, 0x50, 21, 0, },
206 { HI3620_MMC_CLK2, "mmc_clk2", "mmc2_div", CLK_SET_RATE_PARENT, 0x50, 22, 0, },
207 { HI3620_MMC_CLK3, "mmc_clk3", "mmc3_div", CLK_SET_RATE_PARENT, 0x50, 23, 0, },
208 { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PARENT, 0x50, 24, 0, },
209};
210
211static void __init hi3620_clk_init(struct device_node *np)
212{
1/*
2 * Hisilicon Hi3620 clock driver
3 *
4 * Copyright (c) 2012-2013 Hisilicon Limited.
5 * Copyright (c) 2012-2013 Linaro Limited.
6 *
7 * Author: Haojian Zhuang <haojian.zhuang@linaro.org>
8 * Xin Li <li.xin@linaro.org>

--- 196 unchanged lines hidden (view full) ---

205 { HI3620_MMC_CLK1, "mmc_clk1", "mmc1_mux2", CLK_SET_RATE_PARENT, 0x50, 21, 0, },
206 { HI3620_MMC_CLK2, "mmc_clk2", "mmc2_div", CLK_SET_RATE_PARENT, 0x50, 22, 0, },
207 { HI3620_MMC_CLK3, "mmc_clk3", "mmc3_div", CLK_SET_RATE_PARENT, 0x50, 23, 0, },
208 { HI3620_MCU_CLK, "mcu_clk", "acp_clk", CLK_SET_RATE_PARENT, 0x50, 24, 0, },
209};
210
211static void __init hi3620_clk_init(struct device_node *np)
212{
213 void __iomem *base;
213 struct hisi_clock_data *clk_data;
214
214
215 if (np) {
216 base = of_iomap(np, 0);
217 if (!base) {
218 pr_err("failed to map Hi3620 clock registers\n");
219 return;
220 }
221 } else {
222 pr_err("failed to find Hi3620 clock node in DTS\n");
215 clk_data = hisi_clk_init(np, HI3620_NR_CLKS);
216 if (!clk_data)
223 return;
217 return;
224 }
225
218
226 hisi_clk_init(np, HI3620_NR_CLKS);
227
228 hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,
229 ARRAY_SIZE(hi3620_fixed_rate_clks),
219 hisi_clk_register_fixed_rate(hi3620_fixed_rate_clks,
220 ARRAY_SIZE(hi3620_fixed_rate_clks),
230 base);
221 clk_data);
231 hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
232 ARRAY_SIZE(hi3620_fixed_factor_clks),
222 hisi_clk_register_fixed_factor(hi3620_fixed_factor_clks,
223 ARRAY_SIZE(hi3620_fixed_factor_clks),
233 base);
224 clk_data);
234 hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
225 hisi_clk_register_mux(hi3620_mux_clks, ARRAY_SIZE(hi3620_mux_clks),
235 base);
226 clk_data);
236 hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
227 hisi_clk_register_divider(hi3620_div_clks, ARRAY_SIZE(hi3620_div_clks),
237 base);
228 clk_data);
238 hisi_clk_register_gate_sep(hi3620_seperated_gate_clks,
239 ARRAY_SIZE(hi3620_seperated_gate_clks),
229 hisi_clk_register_gate_sep(hi3620_seperated_gate_clks,
230 ARRAY_SIZE(hi3620_seperated_gate_clks),
240 base);
231 clk_data);
241}
242CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);
232}
233CLK_OF_DECLARE(hi3620_clk, "hisilicon,hi3620-clock", hi3620_clk_init);