clk.c (bf6d43d7232511d4aadb634ec97fcbe5d49ee120) clk.c (03813d9b7d4368d4a8c9bb8f5a2a1e23dac8f1b5)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 *
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
7 */
8

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2309int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
2310{
2311 int ret = 0;
2312 unsigned long old_min, old_max, rate;
2313
2314 if (!clk)
2315 return 0;
2316
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
4 * Copyright (C) 2011-2012 Linaro Ltd <mturquette@linaro.org>
5 *
6 * Standard functionality for the common clock API. See Documentation/driver-api/clk.rst
7 */
8

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2309int clk_set_rate_range(struct clk *clk, unsigned long min, unsigned long max)
2310{
2311 int ret = 0;
2312 unsigned long old_min, old_max, rate;
2313
2314 if (!clk)
2315 return 0;
2316
2317 trace_clk_set_rate_range(clk->core, min, max);
2318
2317 if (min > max) {
2318 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
2319 __func__, clk->core->name, clk->dev_id, clk->con_id,
2320 min, max);
2321 return -EINVAL;
2322 }
2323
2324 clk_prepare_lock();

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2376 *
2377 * Returns success (0) or negative errno.
2378 */
2379int clk_set_min_rate(struct clk *clk, unsigned long rate)
2380{
2381 if (!clk)
2382 return 0;
2383
2319 if (min > max) {
2320 pr_err("%s: clk %s dev %s con %s: invalid range [%lu, %lu]\n",
2321 __func__, clk->core->name, clk->dev_id, clk->con_id,
2322 min, max);
2323 return -EINVAL;
2324 }
2325
2326 clk_prepare_lock();

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2378 *
2379 * Returns success (0) or negative errno.
2380 */
2381int clk_set_min_rate(struct clk *clk, unsigned long rate)
2382{
2383 if (!clk)
2384 return 0;
2385
2386 trace_clk_set_min_rate(clk->core, rate);
2387
2384 return clk_set_rate_range(clk, rate, clk->max_rate);
2385}
2386EXPORT_SYMBOL_GPL(clk_set_min_rate);
2387
2388/**
2389 * clk_set_max_rate - set a maximum clock rate for a clock source
2390 * @clk: clock source
2391 * @rate: desired maximum clock rate in Hz, inclusive
2392 *
2393 * Returns success (0) or negative errno.
2394 */
2395int clk_set_max_rate(struct clk *clk, unsigned long rate)
2396{
2397 if (!clk)
2398 return 0;
2399
2388 return clk_set_rate_range(clk, rate, clk->max_rate);
2389}
2390EXPORT_SYMBOL_GPL(clk_set_min_rate);
2391
2392/**
2393 * clk_set_max_rate - set a maximum clock rate for a clock source
2394 * @clk: clock source
2395 * @rate: desired maximum clock rate in Hz, inclusive
2396 *
2397 * Returns success (0) or negative errno.
2398 */
2399int clk_set_max_rate(struct clk *clk, unsigned long rate)
2400{
2401 if (!clk)
2402 return 0;
2403
2404 trace_clk_set_max_rate(clk->core, rate);
2405
2400 return clk_set_rate_range(clk, clk->min_rate, rate);
2401}
2402EXPORT_SYMBOL_GPL(clk_set_max_rate);
2403
2404/**
2405 * clk_get_parent - return the parent of a clk
2406 * @clk: the clk whose parent gets returned
2407 *

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2926 clk_core_get_accuracy_recalc(c));
2927
2928 phase = clk_core_get_phase(c);
2929 if (phase >= 0)
2930 seq_printf(s, "%5d", phase);
2931 else
2932 seq_puts(s, "-----");
2933
2406 return clk_set_rate_range(clk, clk->min_rate, rate);
2407}
2408EXPORT_SYMBOL_GPL(clk_set_max_rate);
2409
2410/**
2411 * clk_get_parent - return the parent of a clk
2412 * @clk: the clk whose parent gets returned
2413 *

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2932 clk_core_get_accuracy_recalc(c));
2933
2934 phase = clk_core_get_phase(c);
2935 if (phase >= 0)
2936 seq_printf(s, "%5d", phase);
2937 else
2938 seq_puts(s, "-----");
2939
2934 seq_printf(s, " %6d", clk_core_get_scaled_duty_cycle(c, 100000));
2935
2936 if (c->ops->is_enabled)
2937 seq_printf(s, " %9c\n", clk_core_is_enabled(c) ? 'Y' : 'N');
2938 else if (!c->ops->enable)
2939 seq_printf(s, " %9c\n", 'Y');
2940 else
2941 seq_printf(s, " %9c\n", '?');
2940 seq_printf(s, " %6d\n", clk_core_get_scaled_duty_cycle(c, 100000));
2942}
2943
2944static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
2945 int level)
2946{
2947 struct clk_core *child;
2948
2949 clk_summary_show_one(s, c, level);
2950
2951 hlist_for_each_entry(child, &c->children, child_node)
2952 clk_summary_show_subtree(s, child, level + 1);
2953}
2954
2955static int clk_summary_show(struct seq_file *s, void *data)
2956{
2957 struct clk_core *c;
2958 struct hlist_head **lists = (struct hlist_head **)s->private;
2959
2941}
2942
2943static void clk_summary_show_subtree(struct seq_file *s, struct clk_core *c,
2944 int level)
2945{
2946 struct clk_core *child;
2947
2948 clk_summary_show_one(s, c, level);
2949
2950 hlist_for_each_entry(child, &c->children, child_node)
2951 clk_summary_show_subtree(s, child, level + 1);
2952}
2953
2954static int clk_summary_show(struct seq_file *s, void *data)
2955{
2956 struct clk_core *c;
2957 struct hlist_head **lists = (struct hlist_head **)s->private;
2958
2960 seq_puts(s, " enable prepare protect duty hardware\n");
2961 seq_puts(s, " clock count count count rate accuracy phase cycle enable\n");
2962 seq_puts(s, "-------------------------------------------------------------------------------------------------------\n");
2959 seq_puts(s, " enable prepare protect duty\n");
2960 seq_puts(s, " clock count count count rate accuracy phase cycle\n");
2961 seq_puts(s, "---------------------------------------------------------------------------------------------\n");
2963
2964 clk_prepare_lock();
2965
2966 for (; *lists; lists++)
2967 hlist_for_each_entry(c, *lists, child_node)
2968 clk_summary_show_subtree(s, c, 0);
2969
2970 clk_prepare_unlock();

--- 2063 unchanged lines hidden --- 		2962
2963 clk_prepare_lock();
2964
2965 for (; *lists; lists++)
2966 hlist_for_each_entry(c, *lists, child_node)
2967 clk_summary_show_subtree(s, c, 0);
2968
2969 clk_prepare_unlock();

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