clk-xgene.c (858a0d7eb5300b5f620d98ab3c4b96c9d5f19131) clk-xgene.c (1667393126d7c51fad8b3cb9d3798e8e0367e2ec)
1/*
2 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
3 *
4 * Copyright (c) 2013, Applied Micro Circuits Corporation
5 * Author: Loc Ho <lho@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

--- 178 unchanged lines hidden (view full) ---

187{
188 const char *clk_name = np->full_name;
189 struct clk *clk;
190 void __iomem *reg;
191 int version = xgene_pllclk_version(np);
192
193 reg = of_iomap(np, 0);
194 if (reg == NULL) {
1/*
2 * clk-xgene.c - AppliedMicro X-Gene Clock Interface
3 *
4 * Copyright (c) 2013, Applied Micro Circuits Corporation
5 * Author: Loc Ho <lho@apm.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as

--- 178 unchanged lines hidden (view full) ---

187{
188 const char *clk_name = np->full_name;
189 struct clk *clk;
190 void __iomem *reg;
191 int version = xgene_pllclk_version(np);
192
193 reg = of_iomap(np, 0);
194 if (reg == NULL) {
195 pr_err("Unable to map CSR register for %s\n", np->full_name);
195 pr_err("Unable to map CSR register for %pOF\n", np);
196 return;
197 }
198 of_property_read_string(np, "clock-output-names", &clk_name);
199 clk = xgene_register_clk_pll(NULL,
200 clk_name, of_clk_get_parent_name(np, 0),
201 0, reg, 0, pll_type, &clk_lock,
202 version);
203 if (!IS_ERR(clk)) {

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404
405 /* Check if the entry is disabled */
406 if (!of_device_is_available(np))
407 return;
408
409 /* Parse the DTS register for resource */
410 rc = of_address_to_resource(np, 0, &res);
411 if (rc != 0) {
196 return;
197 }
198 of_property_read_string(np, "clock-output-names", &clk_name);
199 clk = xgene_register_clk_pll(NULL,
200 clk_name, of_clk_get_parent_name(np, 0),
201 0, reg, 0, pll_type, &clk_lock,
202 version);
203 if (!IS_ERR(clk)) {

--- 200 unchanged lines hidden (view full) ---

404
405 /* Check if the entry is disabled */
406 if (!of_device_is_available(np))
407 return;
408
409 /* Parse the DTS register for resource */
410 rc = of_address_to_resource(np, 0, &res);
411 if (rc != 0) {
412 pr_err("no DTS register for %s\n", np->full_name);
412 pr_err("no DTS register for %pOF\n", np);
413 return;
414 }
415 csr_reg = of_iomap(np, 0);
416 if (!csr_reg) {
413 return;
414 }
415 csr_reg = of_iomap(np, 0);
416 if (!csr_reg) {
417 pr_err("Unable to map resource for %s\n", np->full_name);
417 pr_err("Unable to map resource for %pOF\n", np);
418 return;
419 }
420 of_property_read_string(np, "clock-output-names", &clk_name);
421
422 denom = BIT(XGENE_CLK_PMD_WIDTH);
423 flags |= XGENE_CLK_PMD_SCALE_INVERTED;
424
425 clk = xgene_register_clk_pmd(NULL, clk_name,

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698 /* Parse the DTS register for resource */
699 parameters.csr_reg = NULL;
700 parameters.divider_reg = NULL;
701 for (i = 0; i < 2; i++) {
702 void __iomem *map_res;
703 rc = of_address_to_resource(np, i, &res);
704 if (rc != 0) {
705 if (i == 0) {
418 return;
419 }
420 of_property_read_string(np, "clock-output-names", &clk_name);
421
422 denom = BIT(XGENE_CLK_PMD_WIDTH);
423 flags |= XGENE_CLK_PMD_SCALE_INVERTED;
424
425 clk = xgene_register_clk_pmd(NULL, clk_name,

--- 272 unchanged lines hidden (view full) ---

698 /* Parse the DTS register for resource */
699 parameters.csr_reg = NULL;
700 parameters.divider_reg = NULL;
701 for (i = 0; i < 2; i++) {
702 void __iomem *map_res;
703 rc = of_address_to_resource(np, i, &res);
704 if (rc != 0) {
705 if (i == 0) {
706 pr_err("no DTS register for %s\n",
707 np->full_name);
706 pr_err("no DTS register for %pOF\n", np);
708 return;
709 }
710 break;
711 }
712 map_res = of_iomap(np, i);
713 if (map_res == NULL) {
707 return;
708 }
709 break;
710 }
711 map_res = of_iomap(np, i);
712 if (map_res == NULL) {
714 pr_err("Unable to map resource %d for %s\n",
715 i, np->full_name);
713 pr_err("Unable to map resource %d for %pOF\n", i, np);
716 goto err;
717 }
718 if (strcmp(res.name, "div-reg") == 0)
719 parameters.divider_reg = map_res;
720 else /* if (strcmp(res->name, "csr-reg") == 0) */
721 parameters.csr_reg = map_res;
722 }
723 if (of_property_read_u32(np, "csr-offset", &parameters.reg_csr_offset))

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742
743 clk = xgene_register_clk(NULL, clk_name,
744 of_clk_get_parent_name(np, 0), &parameters, &clk_lock);
745 if (IS_ERR(clk))
746 goto err;
747 pr_debug("Add %s clock\n", clk_name);
748 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
749 if (rc != 0)
714 goto err;
715 }
716 if (strcmp(res.name, "div-reg") == 0)
717 parameters.divider_reg = map_res;
718 else /* if (strcmp(res->name, "csr-reg") == 0) */
719 parameters.csr_reg = map_res;
720 }
721 if (of_property_read_u32(np, "csr-offset", &parameters.reg_csr_offset))

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740
741 clk = xgene_register_clk(NULL, clk_name,
742 of_clk_get_parent_name(np, 0), &parameters, &clk_lock);
743 if (IS_ERR(clk))
744 goto err;
745 pr_debug("Add %s clock\n", clk_name);
746 rc = of_clk_add_provider(np, of_clk_src_simple_get, clk);
747 if (rc != 0)
750 pr_err("%s: could register provider clk %s\n", __func__,
751 np->full_name);
748 pr_err("%s: could register provider clk %pOF\n", __func__, np);
752
753 return;
754
755err:
756 if (parameters.csr_reg)
757 iounmap(parameters.csr_reg);
758 if (parameters.divider_reg)
759 iounmap(parameters.divider_reg);
760}
761
762CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
763CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
764CLK_OF_DECLARE(xgene_pmd_clock, "apm,xgene-pmd-clock", xgene_pmdclk_init);
765CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock",
766 xgene_socpllclk_init);
767CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock",
768 xgene_pcppllclk_init);
769CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);
749
750 return;
751
752err:
753 if (parameters.csr_reg)
754 iounmap(parameters.csr_reg);
755 if (parameters.divider_reg)
756 iounmap(parameters.divider_reg);
757}
758
759CLK_OF_DECLARE(xgene_socpll_clock, "apm,xgene-socpll-clock", xgene_socpllclk_init);
760CLK_OF_DECLARE(xgene_pcppll_clock, "apm,xgene-pcppll-clock", xgene_pcppllclk_init);
761CLK_OF_DECLARE(xgene_pmd_clock, "apm,xgene-pmd-clock", xgene_pmdclk_init);
762CLK_OF_DECLARE(xgene_socpll_v2_clock, "apm,xgene-socpll-v2-clock",
763 xgene_socpllclk_init);
764CLK_OF_DECLARE(xgene_pcppll_v2_clock, "apm,xgene-pcppll-v2-clock",
765 xgene_pcppllclk_init);
766CLK_OF_DECLARE(xgene_dev_clock, "apm,xgene-device-clock", xgene_devclk_init);