clk-conf.c (1ed7d32763857fbdc8e406352404538e41050d22) clk-conf.c (1667393126d7c51fad8b3cb9d3798e8e0367e2ec)
1/*
2 * Copyright (C) 2014 Samsung Electronics Co., Ltd.
3 * Sylwester Nawrocki <s.nawrocki@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */

--- 9 unchanged lines hidden (view full) ---

18{
19 struct of_phandle_args clkspec;
20 int index, rc, num_parents;
21 struct clk *clk, *pclk;
22
23 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
24 "#clock-cells");
25 if (num_parents == -EINVAL)
1/*
2 * Copyright (C) 2014 Samsung Electronics Co., Ltd.
3 * Sylwester Nawrocki <s.nawrocki@samsung.com>
4 *
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
8 */

--- 9 unchanged lines hidden (view full) ---

18{
19 struct of_phandle_args clkspec;
20 int index, rc, num_parents;
21 struct clk *clk, *pclk;
22
23 num_parents = of_count_phandle_with_args(node, "assigned-clock-parents",
24 "#clock-cells");
25 if (num_parents == -EINVAL)
26 pr_err("clk: invalid value of clock-parents property at %s\n",
27 node->full_name);
26 pr_err("clk: invalid value of clock-parents property at %pOF\n",
27 node);
28
29 for (index = 0; index < num_parents; index++) {
30 rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
31 "#clock-cells", index, &clkspec);
32 if (rc < 0) {
33 /* skip empty (null) phandles */
34 if (rc == -ENOENT)
35 continue;
36 else
37 return rc;
38 }
39 if (clkspec.np == node && !clk_supplier)
40 return 0;
41 pclk = of_clk_get_from_provider(&clkspec);
42 if (IS_ERR(pclk)) {
43 if (PTR_ERR(pclk) != -EPROBE_DEFER)
28
29 for (index = 0; index < num_parents; index++) {
30 rc = of_parse_phandle_with_args(node, "assigned-clock-parents",
31 "#clock-cells", index, &clkspec);
32 if (rc < 0) {
33 /* skip empty (null) phandles */
34 if (rc == -ENOENT)
35 continue;
36 else
37 return rc;
38 }
39 if (clkspec.np == node && !clk_supplier)
40 return 0;
41 pclk = of_clk_get_from_provider(&clkspec);
42 if (IS_ERR(pclk)) {
43 if (PTR_ERR(pclk) != -EPROBE_DEFER)
44 pr_warn("clk: couldn't get parent clock %d for %s\n",
45 index, node->full_name);
44 pr_warn("clk: couldn't get parent clock %d for %pOF\n",
45 index, node);
46 return PTR_ERR(pclk);
47 }
48
49 rc = of_parse_phandle_with_args(node, "assigned-clocks",
50 "#clock-cells", index, &clkspec);
51 if (rc < 0)
52 goto err;
53 if (clkspec.np == node && !clk_supplier) {
54 rc = 0;
55 goto err;
56 }
57 clk = of_clk_get_from_provider(&clkspec);
58 if (IS_ERR(clk)) {
59 if (PTR_ERR(clk) != -EPROBE_DEFER)
46 return PTR_ERR(pclk);
47 }
48
49 rc = of_parse_phandle_with_args(node, "assigned-clocks",
50 "#clock-cells", index, &clkspec);
51 if (rc < 0)
52 goto err;
53 if (clkspec.np == node && !clk_supplier) {
54 rc = 0;
55 goto err;
56 }
57 clk = of_clk_get_from_provider(&clkspec);
58 if (IS_ERR(clk)) {
59 if (PTR_ERR(clk) != -EPROBE_DEFER)
60 pr_warn("clk: couldn't get assigned clock %d for %s\n",
61 index, node->full_name);
60 pr_warn("clk: couldn't get assigned clock %d for %pOF\n",
61 index, node);
62 rc = PTR_ERR(clk);
63 goto err;
64 }
65
66 rc = clk_set_parent(clk, pclk);
67 if (rc < 0)
68 pr_err("clk: failed to reparent %s to %s: %d\n",
69 __clk_get_name(clk), __clk_get_name(pclk), rc);

--- 27 unchanged lines hidden (view full) ---

97 return rc;
98 }
99 if (clkspec.np == node && !clk_supplier)
100 return 0;
101
102 clk = of_clk_get_from_provider(&clkspec);
103 if (IS_ERR(clk)) {
104 if (PTR_ERR(clk) != -EPROBE_DEFER)
62 rc = PTR_ERR(clk);
63 goto err;
64 }
65
66 rc = clk_set_parent(clk, pclk);
67 if (rc < 0)
68 pr_err("clk: failed to reparent %s to %s: %d\n",
69 __clk_get_name(clk), __clk_get_name(pclk), rc);

--- 27 unchanged lines hidden (view full) ---

97 return rc;
98 }
99 if (clkspec.np == node && !clk_supplier)
100 return 0;
101
102 clk = of_clk_get_from_provider(&clkspec);
103 if (IS_ERR(clk)) {
104 if (PTR_ERR(clk) != -EPROBE_DEFER)
105 pr_warn("clk: couldn't get clock %d for %s\n",
106 index, node->full_name);
105 pr_warn("clk: couldn't get clock %d for %pOF\n",
106 index, node);
107 return PTR_ERR(clk);
108 }
109
110 rc = clk_set_rate(clk, rate);
111 if (rc < 0)
112 pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n",
113 __clk_get_name(clk), rate, rc,
114 clk_get_rate(clk));

--- 33 unchanged lines hidden --- 		107 return PTR_ERR(clk);
108 }
109
110 rc = clk_set_rate(clk, rate);
111 if (rc < 0)
112 pr_err("clk: couldn't set %s clk rate to %u (%d), current rate: %lu\n",
113 __clk_get_name(clk), rate, rc,
114 clk_get_rate(clk));

--- 33 unchanged lines hidden ---