bg2q.c (858a0d7eb5300b5f620d98ab3c4b96c9d5f19131) bg2q.c (1667393126d7c51fad8b3cb9d3798e8e0367e2ec)
1/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 *
4 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

--- 290 unchanged lines hidden (view full) ---

299 sizeof(*clk_data->hws) * MAX_CLKS, GFP_KERNEL);
300 if (!clk_data)
301 return;
302 clk_data->num = MAX_CLKS;
303 hws = clk_data->hws;
304
305 gbase = of_iomap(parent_np, 0);
306 if (!gbase) {
1/*
2 * Copyright (c) 2014 Marvell Technology Group Ltd.
3 *
4 * Alexandre Belloni <alexandre.belloni@free-electrons.com>
5 * Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms and conditions of the GNU General Public License,

--- 290 unchanged lines hidden (view full) ---

299 sizeof(*clk_data->hws) * MAX_CLKS, GFP_KERNEL);
300 if (!clk_data)
301 return;
302 clk_data->num = MAX_CLKS;
303 hws = clk_data->hws;
304
305 gbase = of_iomap(parent_np, 0);
306 if (!gbase) {
307 pr_err("%s: Unable to map global base\n", np->full_name);
307 pr_err("%pOF: Unable to map global base\n", np);
308 return;
309 }
310
311 /* BG2Q CPU PLL is not part of global registers */
312 cpupll_base = of_iomap(parent_np, 1);
313 if (!cpupll_base) {
308 return;
309 }
310
311 /* BG2Q CPU PLL is not part of global registers */
312 cpupll_base = of_iomap(parent_np, 1);
313 if (!cpupll_base) {
314 pr_err("%s: Unable to map cpupll base\n", np->full_name);
314 pr_err("%pOF: Unable to map cpupll base\n", np);
315 iounmap(gbase);
316 return;
317 }
318
319 /* overwrite default clock names with DT provided ones */
320 clk = of_clk_get_by_name(np, clk_names[REFCLK]);
321 if (!IS_ERR(clk)) {
322 clk_names[REFCLK] = __clk_get_name(clk);

--- 48 unchanged lines hidden (view full) ---

371 hws[CLKID_TWD] =
372 clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
373
374 /* check for errors on leaf clocks */
375 for (n = 0; n < MAX_CLKS; n++) {
376 if (!IS_ERR(hws[n]))
377 continue;
378
315 iounmap(gbase);
316 return;
317 }
318
319 /* overwrite default clock names with DT provided ones */
320 clk = of_clk_get_by_name(np, clk_names[REFCLK]);
321 if (!IS_ERR(clk)) {
322 clk_names[REFCLK] = __clk_get_name(clk);

--- 48 unchanged lines hidden (view full) ---

371 hws[CLKID_TWD] =
372 clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
373
374 /* check for errors on leaf clocks */
375 for (n = 0; n < MAX_CLKS; n++) {
376 if (!IS_ERR(hws[n]))
377 continue;
378
379 pr_err("%s: Unable to register leaf clock %d\n",
380 np->full_name, n);
379 pr_err("%pOF: Unable to register leaf clock %d\n", np, n);
381 goto bg2q_fail;
382 }
383
384 /* register clk-provider */
385 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
386
387 return;
388
389bg2q_fail:
390 iounmap(cpupll_base);
391 iounmap(gbase);
392}
393CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",
394 berlin2q_clock_setup);
380 goto bg2q_fail;
381 }
382
383 /* register clk-provider */
384 of_clk_add_hw_provider(np, of_clk_hw_onecell_get, clk_data);
385
386 return;
387
388bg2q_fail:
389 iounmap(cpupll_base);
390 iounmap(gbase);
391}
392CLK_OF_DECLARE(berlin2q_clk, "marvell,berlin2q-clk",
393 berlin2q_clock_setup);