tpm.h (58472f5cd4f6ff02488c8da3cdbf719e9dd21e48) tpm.h (745b361e989af21ad40811c2586b60229f870a68)
1/*
2 * Copyright (C) 2004 IBM Corporation
3 * Copyright (C) 2015 Intel Corporation
4 *
5 * Authors:
6 * Leendert van Doorn <leendert@watson.ibm.com>
7 * Dave Safford <safford@watson.ibm.com>
8 * Reiner Sailer <sailer@watson.ibm.com>

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84};
85
86enum tpm2_structures {
87 TPM2_ST_NO_SESSIONS = 0x8001,
88 TPM2_ST_SESSIONS = 0x8002,
89};
90
91enum tpm2_return_codes {
1/*
2 * Copyright (C) 2004 IBM Corporation
3 * Copyright (C) 2015 Intel Corporation
4 *
5 * Authors:
6 * Leendert van Doorn <leendert@watson.ibm.com>
7 * Dave Safford <safford@watson.ibm.com>
8 * Reiner Sailer <sailer@watson.ibm.com>

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84};
85
86enum tpm2_structures {
87 TPM2_ST_NO_SESSIONS = 0x8001,
88 TPM2_ST_SESSIONS = 0x8002,
89};
90
91enum tpm2_return_codes {
92 TPM2_RC_SUCCESS = 0x0000,
92 TPM2_RC_HASH = 0x0083, /* RC_FMT1 */
93 TPM2_RC_HASH = 0x0083, /* RC_FMT1 */
94 TPM2_RC_HANDLE = 0x008B,
93 TPM2_RC_INITIALIZE = 0x0100, /* RC_VER1 */
94 TPM2_RC_DISABLED = 0x0120,
95 TPM2_RC_TESTING = 0x090A, /* RC_WARN */
95 TPM2_RC_INITIALIZE = 0x0100, /* RC_VER1 */
96 TPM2_RC_DISABLED = 0x0120,
97 TPM2_RC_TESTING = 0x090A, /* RC_WARN */
98 TPM2_RC_REFERENCE_H0 = 0x0910,
96};
97
98enum tpm2_algorithms {
99 TPM2_ALG_ERROR = 0x0000,
100 TPM2_ALG_SHA1 = 0x0004,
101 TPM2_ALG_KEYEDHASH = 0x0008,
102 TPM2_ALG_SHA256 = 0x000B,
103 TPM2_ALG_SHA384 = 0x000C,

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109enum tpm2_command_codes {
110 TPM2_CC_FIRST = 0x011F,
111 TPM2_CC_SELF_TEST = 0x0143,
112 TPM2_CC_STARTUP = 0x0144,
113 TPM2_CC_SHUTDOWN = 0x0145,
114 TPM2_CC_CREATE = 0x0153,
115 TPM2_CC_LOAD = 0x0157,
116 TPM2_CC_UNSEAL = 0x015E,
99};
100
101enum tpm2_algorithms {
102 TPM2_ALG_ERROR = 0x0000,
103 TPM2_ALG_SHA1 = 0x0004,
104 TPM2_ALG_KEYEDHASH = 0x0008,
105 TPM2_ALG_SHA256 = 0x000B,
106 TPM2_ALG_SHA384 = 0x000C,

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112enum tpm2_command_codes {
113 TPM2_CC_FIRST = 0x011F,
114 TPM2_CC_SELF_TEST = 0x0143,
115 TPM2_CC_STARTUP = 0x0144,
116 TPM2_CC_SHUTDOWN = 0x0145,
117 TPM2_CC_CREATE = 0x0153,
118 TPM2_CC_LOAD = 0x0157,
119 TPM2_CC_UNSEAL = 0x015E,
120 TPM2_CC_CONTEXT_LOAD = 0x0161,
117 TPM2_CC_CONTEXT_SAVE = 0x0162,
118 TPM2_CC_FLUSH_CONTEXT = 0x0165,
119 TPM2_CC_GET_CAPABILITY = 0x017A,
120 TPM2_CC_GET_RANDOM = 0x017B,
121 TPM2_CC_PCR_READ = 0x017E,
122 TPM2_CC_PCR_EXTEND = 0x0182,
123 TPM2_CC_LAST = 0x018F,
124};
125
126enum tpm2_permanent_handles {
127 TPM2_RS_PW = 0x40000009,
128};
129
130enum tpm2_capabilities {
121 TPM2_CC_CONTEXT_SAVE = 0x0162,
122 TPM2_CC_FLUSH_CONTEXT = 0x0165,
123 TPM2_CC_GET_CAPABILITY = 0x017A,
124 TPM2_CC_GET_RANDOM = 0x017B,
125 TPM2_CC_PCR_READ = 0x017E,
126 TPM2_CC_PCR_EXTEND = 0x0182,
127 TPM2_CC_LAST = 0x018F,
128};
129
130enum tpm2_permanent_handles {
131 TPM2_RS_PW = 0x40000009,
132};
133
134enum tpm2_capabilities {
135 TPM2_CAP_HANDLES = 1,
131 TPM2_CAP_COMMANDS = 2,
132 TPM2_CAP_PCRS = 5,
133 TPM2_CAP_TPM_PROPERTIES = 6,
134};
135
136enum tpm2_properties {
137 TPM_PT_TOTAL_COMMANDS = 0x0129,
138};

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148};
149
150#define TPM_VID_INTEL 0x8086
151#define TPM_VID_WINBOND 0x1050
152#define TPM_VID_STM 0x104A
153
154#define TPM_PPI_VERSION_LEN 3
155
136 TPM2_CAP_COMMANDS = 2,
137 TPM2_CAP_PCRS = 5,
138 TPM2_CAP_TPM_PROPERTIES = 6,
139};
140
141enum tpm2_properties {
142 TPM_PT_TOTAL_COMMANDS = 0x0129,
143};

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153};
154
155#define TPM_VID_INTEL 0x8086
156#define TPM_VID_WINBOND 0x1050
157#define TPM_VID_STM 0x104A
158
159#define TPM_PPI_VERSION_LEN 3
160
161struct tpm_space {
162 u32 context_tbl[3];
163 u8 *context_buf;
164};
165
156enum tpm_chip_flags {
157 TPM_CHIP_FLAG_TPM2 = BIT(1),
158 TPM_CHIP_FLAG_IRQ = BIT(2),
159 TPM_CHIP_FLAG_VIRTUAL = BIT(3),
160 TPM_CHIP_FLAG_HAVE_TIMEOUTS = BIT(4),
161};
162
163struct tpm_bios_log {

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206 unsigned int groups_cnt;
207
208 u16 active_banks[7];
209#ifdef CONFIG_ACPI
210 acpi_handle acpi_dev_handle;
211 char ppi_version[TPM_PPI_VERSION_LEN + 1];
212#endif /* CONFIG_ACPI */
213
166enum tpm_chip_flags {
167 TPM_CHIP_FLAG_TPM2 = BIT(1),
168 TPM_CHIP_FLAG_IRQ = BIT(2),
169 TPM_CHIP_FLAG_VIRTUAL = BIT(3),
170 TPM_CHIP_FLAG_HAVE_TIMEOUTS = BIT(4),
171};
172
173struct tpm_bios_log {

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216 unsigned int groups_cnt;
217
218 u16 active_banks[7];
219#ifdef CONFIG_ACPI
220 acpi_handle acpi_dev_handle;
221 char ppi_version[TPM_PPI_VERSION_LEN + 1];
222#endif /* CONFIG_ACPI */
223
224 struct tpm_space work_space;
214 u32 nr_commands;
215 u32 *cc_attrs_tbl;
216};
217
218#define to_tpm_chip(d) container_of(d, struct tpm_chip, dev)
219
220struct tpm_input_header {
221 __be16 tag;

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502extern dev_t tpm_devt;
503extern const struct file_operations tpm_fops;
504extern struct idr dev_nums_idr;
505
506enum tpm_transmit_flags {
507 TPM_TRANSMIT_UNLOCKED = BIT(0),
508};
509
225 u32 nr_commands;
226 u32 *cc_attrs_tbl;
227};
228
229#define to_tpm_chip(d) container_of(d, struct tpm_chip, dev)
230
231struct tpm_input_header {
232 __be16 tag;

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513extern dev_t tpm_devt;
514extern const struct file_operations tpm_fops;
515extern struct idr dev_nums_idr;
516
517enum tpm_transmit_flags {
518 TPM_TRANSMIT_UNLOCKED = BIT(0),
519};
520
510ssize_t tpm_transmit(struct tpm_chip *chip, const u8 *buf, size_t bufsiz,
511 unsigned int flags);
512ssize_t tpm_transmit_cmd(struct tpm_chip *chip, const void *buf, size_t bufsiz,
513 size_t min_rsp_body_len, unsigned int flags,
521ssize_t tpm_transmit(struct tpm_chip *chip, struct tpm_space *space,
522 u8 *buf, size_t bufsiz, unsigned int flags);
523ssize_t tpm_transmit_cmd(struct tpm_chip *chip, struct tpm_space *space,
524 const void *buf, size_t bufsiz,
525 size_t min_rsp_body_length, unsigned int flags,
514 const char *desc);
515ssize_t tpm_getcap(struct tpm_chip *chip, u32 subcap_id, cap_t *cap,
516 const char *desc, size_t min_cap_length);
517int tpm_get_timeouts(struct tpm_chip *);
518int tpm1_auto_startup(struct tpm_chip *chip);
519int tpm_do_selftest(struct tpm_chip *chip);
520unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal);
521int tpm_pm_suspend(struct device *dev);

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566ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id,
567 u32 *value, const char *desc);
568
569int tpm2_auto_startup(struct tpm_chip *chip);
570void tpm2_shutdown(struct tpm_chip *chip, u16 shutdown_type);
571unsigned long tpm2_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal);
572int tpm2_probe(struct tpm_chip *chip);
573int tpm2_find_cc(struct tpm_chip *chip, u32 cc);
526 const char *desc);
527ssize_t tpm_getcap(struct tpm_chip *chip, u32 subcap_id, cap_t *cap,
528 const char *desc, size_t min_cap_length);
529int tpm_get_timeouts(struct tpm_chip *);
530int tpm1_auto_startup(struct tpm_chip *chip);
531int tpm_do_selftest(struct tpm_chip *chip);
532unsigned long tpm_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal);
533int tpm_pm_suspend(struct device *dev);

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578ssize_t tpm2_get_tpm_pt(struct tpm_chip *chip, u32 property_id,
579 u32 *value, const char *desc);
580
581int tpm2_auto_startup(struct tpm_chip *chip);
582void tpm2_shutdown(struct tpm_chip *chip, u16 shutdown_type);
583unsigned long tpm2_calc_ordinal_duration(struct tpm_chip *chip, u32 ordinal);
584int tpm2_probe(struct tpm_chip *chip);
585int tpm2_find_cc(struct tpm_chip *chip, u32 cc);
586int tpm2_init_space(struct tpm_space *space);
587void tpm2_del_space(struct tpm_space *space);
588int tpm2_prepare_space(struct tpm_chip *chip, struct tpm_space *space, u32 cc,
589 u8 *cmd);
590int tpm2_commit_space(struct tpm_chip *chip, struct tpm_space *space,
591 u32 cc, u8 *buf, size_t *bufsiz);
574#endif
592#endif