sata_sil24.c (f632265d0ffb5acf331252d98c64939849d96bb2) sata_sil24.c (97750cebb3000a9cc08f8ce8dc8c7143be7d7201)
1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it

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584 struct sil24_port_priv *pp = ap->private_data;
585 u32 tmp;
586
587 /* clear PMP error status */
588 if (sata_pmp_attached(ap))
589 sil24_clear_pmp(ap);
590
591 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
1/*
2 * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers
3 *
4 * Copyright 2005 Tejun Heo
5 *
6 * Based on preview driver from Silicon Image.
7 *
8 * This program is free software; you can redistribute it and/or modify it

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584 struct sil24_port_priv *pp = ap->private_data;
585 u32 tmp;
586
587 /* clear PMP error status */
588 if (sata_pmp_attached(ap))
589 sil24_clear_pmp(ap);
590
591 writel(PORT_CS_INIT, port + PORT_CTRL_STAT);
592 ata_wait_register(port + PORT_CTRL_STAT,
592 ata_wait_register(ap, port + PORT_CTRL_STAT,
593 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
593 PORT_CS_INIT, PORT_CS_INIT, 10, 100);
594 tmp = ata_wait_register(port + PORT_CTRL_STAT,
594 tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
595 PORT_CS_RDY, 0, 10, 100);
596
597 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
598 pp->do_port_rst = 1;
599 ap->link.eh_context.i.action |= ATA_EH_RESET;
600 return -EIO;
601 }
602

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626 * The barrier is required to ensure that writes to cmd_block reach
627 * the memory before the write to PORT_CMD_ACTIVATE.
628 */
629 wmb();
630 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
631 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
632
633 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
595 PORT_CS_RDY, 0, 10, 100);
596
597 if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) {
598 pp->do_port_rst = 1;
599 ap->link.eh_context.i.action |= ATA_EH_RESET;
600 return -EIO;
601 }
602

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626 * The barrier is required to ensure that writes to cmd_block reach
627 * the memory before the write to PORT_CMD_ACTIVATE.
628 */
629 wmb();
630 writel((u32)paddr, port + PORT_CMD_ACTIVATE);
631 writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4);
632
633 irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT;
634 irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0,
634 irq_stat = ata_wait_register(ap, port + PORT_IRQ_STAT, irq_mask, 0x0,
635 10, timeout_msec);
636
637 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
638 irq_stat >>= PORT_IRQ_RAW_SHIFT;
639
640 if (irq_stat & PORT_IRQ_COMPLETE)
641 rc = 0;
642 else {

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714 /* Sometimes, DEV_RST is not enough to recover the controller.
715 * This happens often after PM DMA CS errata.
716 */
717 if (pp->do_port_rst) {
718 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
719 "state, performing PORT_RST\n");
720
721 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
635 10, timeout_msec);
636
637 writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */
638 irq_stat >>= PORT_IRQ_RAW_SHIFT;
639
640 if (irq_stat & PORT_IRQ_COMPLETE)
641 rc = 0;
642 else {

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714 /* Sometimes, DEV_RST is not enough to recover the controller.
715 * This happens often after PM DMA CS errata.
716 */
717 if (pp->do_port_rst) {
718 ata_port_printk(ap, KERN_WARNING, "controller in dubious "
719 "state, performing PORT_RST\n");
720
721 writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT);
722 msleep(10);
722 ata_msleep(ap, 10);
723 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
723 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
724 ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
724 ata_wait_register(ap, port + PORT_CTRL_STAT, PORT_CS_RDY, 0,
725 10, 5000);
726
727 /* restore port configuration */
728 sil24_config_port(ap);
729 sil24_config_pmp(ap, ap->nr_pmp_links);
730
731 pp->do_port_rst = 0;
732 did_port_rst = 1;
733 }
734
735 /* sil24 does the right thing(tm) without any protection */
736 sata_set_spd(link);
737
738 tout_msec = 100;
739 if (ata_link_online(link))
740 tout_msec = 5000;
741
742 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
725 10, 5000);
726
727 /* restore port configuration */
728 sil24_config_port(ap);
729 sil24_config_pmp(ap, ap->nr_pmp_links);
730
731 pp->do_port_rst = 0;
732 did_port_rst = 1;
733 }
734
735 /* sil24 does the right thing(tm) without any protection */
736 sata_set_spd(link);
737
738 tout_msec = 100;
739 if (ata_link_online(link))
740 tout_msec = 5000;
741
742 writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT);
743 tmp = ata_wait_register(port + PORT_CTRL_STAT,
743 tmp = ata_wait_register(ap, port + PORT_CTRL_STAT,
744 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
745 tout_msec);
746
747 /* SStatus oscillates between zero and valid status after
748 * DEV_RST, debounce it.
749 */
750 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
751 if (rc) {

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1248
1249 /* Initial PHY setting */
1250 writel(0x20c, port + PORT_PHY_CFG);
1251
1252 /* Clear port RST */
1253 tmp = readl(port + PORT_CTRL_STAT);
1254 if (tmp & PORT_CS_PORT_RST) {
1255 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
744 PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10,
745 tout_msec);
746
747 /* SStatus oscillates between zero and valid status after
748 * DEV_RST, debounce it.
749 */
750 rc = sata_link_debounce(link, sata_deb_timing_long, deadline);
751 if (rc) {

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1248
1249 /* Initial PHY setting */
1250 writel(0x20c, port + PORT_PHY_CFG);
1251
1252 /* Clear port RST */
1253 tmp = readl(port + PORT_CTRL_STAT);
1254 if (tmp & PORT_CS_PORT_RST) {
1255 writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR);
1256 tmp = ata_wait_register(port + PORT_CTRL_STAT,
1256 tmp = ata_wait_register(NULL, port + PORT_CTRL_STAT,
1257 PORT_CS_PORT_RST,
1258 PORT_CS_PORT_RST, 10, 100);
1259 if (tmp & PORT_CS_PORT_RST)
1260 dev_printk(KERN_ERR, host->dev,
1261 "failed to clear port RST\n");
1262 }
1263
1264 /* configure port */

--- 143 unchanged lines hidden --- 		1257 PORT_CS_PORT_RST,
1258 PORT_CS_PORT_RST, 10, 100);
1259 if (tmp & PORT_CS_PORT_RST)
1260 dev_printk(KERN_ERR, host->dev,
1261 "failed to clear port RST\n");
1262 }
1263
1264 /* configure port */

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