sata_nv.c (f2fb344beadf79f9d265c3fc60e8399bbf917a4d) sata_nv.c (9a829ccfc833269bdb85751f5048288ab93678ac)
1/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify

--- 355 unchanged lines hidden (view full) ---

364 .bmdma_status = ata_bmdma_status,
365 .qc_prep = ata_qc_prep,
366 .qc_issue = ata_qc_issue_prot,
367 .freeze = ata_bmdma_freeze,
368 .thaw = ata_bmdma_thaw,
369 .error_handler = nv_error_handler,
370 .post_internal_cmd = ata_bmdma_post_internal_cmd,
371 .data_xfer = ata_data_xfer,
1/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify

--- 355 unchanged lines hidden (view full) ---

364 .bmdma_status = ata_bmdma_status,
365 .qc_prep = ata_qc_prep,
366 .qc_issue = ata_qc_issue_prot,
367 .freeze = ata_bmdma_freeze,
368 .thaw = ata_bmdma_thaw,
369 .error_handler = nv_error_handler,
370 .post_internal_cmd = ata_bmdma_post_internal_cmd,
371 .data_xfer = ata_data_xfer,
372 .irq_handler = nv_generic_interrupt,
373 .irq_clear = ata_bmdma_irq_clear,
374 .irq_on = ata_irq_on,
375 .irq_ack = ata_irq_ack,
376 .scr_read = nv_scr_read,
377 .scr_write = nv_scr_write,
378 .port_start = ata_port_start,
379};
380

--- 10 unchanged lines hidden (view full) ---

391 .bmdma_status = ata_bmdma_status,
392 .qc_prep = ata_qc_prep,
393 .qc_issue = ata_qc_issue_prot,
394 .freeze = nv_nf2_freeze,
395 .thaw = nv_nf2_thaw,
396 .error_handler = nv_error_handler,
397 .post_internal_cmd = ata_bmdma_post_internal_cmd,
398 .data_xfer = ata_data_xfer,
372 .irq_clear = ata_bmdma_irq_clear,
373 .irq_on = ata_irq_on,
374 .irq_ack = ata_irq_ack,
375 .scr_read = nv_scr_read,
376 .scr_write = nv_scr_write,
377 .port_start = ata_port_start,
378};
379

--- 10 unchanged lines hidden (view full) ---

390 .bmdma_status = ata_bmdma_status,
391 .qc_prep = ata_qc_prep,
392 .qc_issue = ata_qc_issue_prot,
393 .freeze = nv_nf2_freeze,
394 .thaw = nv_nf2_thaw,
395 .error_handler = nv_error_handler,
396 .post_internal_cmd = ata_bmdma_post_internal_cmd,
397 .data_xfer = ata_data_xfer,
399 .irq_handler = nv_nf2_interrupt,
400 .irq_clear = ata_bmdma_irq_clear,
401 .irq_on = ata_irq_on,
402 .irq_ack = ata_irq_ack,
403 .scr_read = nv_scr_read,
404 .scr_write = nv_scr_write,
405 .port_start = ata_port_start,
406};
407

--- 10 unchanged lines hidden (view full) ---

418 .bmdma_status = ata_bmdma_status,
419 .qc_prep = ata_qc_prep,
420 .qc_issue = ata_qc_issue_prot,
421 .freeze = nv_ck804_freeze,
422 .thaw = nv_ck804_thaw,
423 .error_handler = nv_error_handler,
424 .post_internal_cmd = ata_bmdma_post_internal_cmd,
425 .data_xfer = ata_data_xfer,
398 .irq_clear = ata_bmdma_irq_clear,
399 .irq_on = ata_irq_on,
400 .irq_ack = ata_irq_ack,
401 .scr_read = nv_scr_read,
402 .scr_write = nv_scr_write,
403 .port_start = ata_port_start,
404};
405

--- 10 unchanged lines hidden (view full) ---

416 .bmdma_status = ata_bmdma_status,
417 .qc_prep = ata_qc_prep,
418 .qc_issue = ata_qc_issue_prot,
419 .freeze = nv_ck804_freeze,
420 .thaw = nv_ck804_thaw,
421 .error_handler = nv_error_handler,
422 .post_internal_cmd = ata_bmdma_post_internal_cmd,
423 .data_xfer = ata_data_xfer,
426 .irq_handler = nv_ck804_interrupt,
427 .irq_clear = ata_bmdma_irq_clear,
428 .irq_on = ata_irq_on,
429 .irq_ack = ata_irq_ack,
430 .scr_read = nv_scr_read,
431 .scr_write = nv_scr_write,
432 .port_start = ata_port_start,
433 .host_stop = nv_ck804_host_stop,
434};

--- 12 unchanged lines hidden (view full) ---

447 .bmdma_status = ata_bmdma_status,
448 .qc_prep = nv_adma_qc_prep,
449 .qc_issue = nv_adma_qc_issue,
450 .freeze = nv_ck804_freeze,
451 .thaw = nv_ck804_thaw,
452 .error_handler = nv_adma_error_handler,
453 .post_internal_cmd = nv_adma_post_internal_cmd,
454 .data_xfer = ata_data_xfer,
424 .irq_clear = ata_bmdma_irq_clear,
425 .irq_on = ata_irq_on,
426 .irq_ack = ata_irq_ack,
427 .scr_read = nv_scr_read,
428 .scr_write = nv_scr_write,
429 .port_start = ata_port_start,
430 .host_stop = nv_ck804_host_stop,
431};

--- 12 unchanged lines hidden (view full) ---

444 .bmdma_status = ata_bmdma_status,
445 .qc_prep = nv_adma_qc_prep,
446 .qc_issue = nv_adma_qc_issue,
447 .freeze = nv_ck804_freeze,
448 .thaw = nv_ck804_thaw,
449 .error_handler = nv_adma_error_handler,
450 .post_internal_cmd = nv_adma_post_internal_cmd,
451 .data_xfer = ata_data_xfer,
455 .irq_handler = nv_adma_interrupt,
456 .irq_clear = nv_adma_irq_clear,
457 .irq_on = ata_irq_on,
458 .irq_ack = ata_irq_ack,
459 .scr_read = nv_scr_read,
460 .scr_write = nv_scr_write,
461 .port_start = nv_adma_port_start,
462 .port_stop = nv_adma_port_stop,
463#ifdef CONFIG_PM

--- 8 unchanged lines hidden (view full) ---

472 {
473 .sht = &nv_sht,
474 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
475 ATA_FLAG_HRST_TO_RESUME,
476 .pio_mask = NV_PIO_MASK,
477 .mwdma_mask = NV_MWDMA_MASK,
478 .udma_mask = NV_UDMA_MASK,
479 .port_ops = &nv_generic_ops,
452 .irq_clear = nv_adma_irq_clear,
453 .irq_on = ata_irq_on,
454 .irq_ack = ata_irq_ack,
455 .scr_read = nv_scr_read,
456 .scr_write = nv_scr_write,
457 .port_start = nv_adma_port_start,
458 .port_stop = nv_adma_port_stop,
459#ifdef CONFIG_PM

--- 8 unchanged lines hidden (view full) ---

468 {
469 .sht = &nv_sht,
470 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
471 ATA_FLAG_HRST_TO_RESUME,
472 .pio_mask = NV_PIO_MASK,
473 .mwdma_mask = NV_MWDMA_MASK,
474 .udma_mask = NV_UDMA_MASK,
475 .port_ops = &nv_generic_ops,
476 .irq_handler = nv_generic_interrupt,
480 },
481 /* nforce2/3 */
482 {
483 .sht = &nv_sht,
484 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
485 ATA_FLAG_HRST_TO_RESUME,
486 .pio_mask = NV_PIO_MASK,
487 .mwdma_mask = NV_MWDMA_MASK,
488 .udma_mask = NV_UDMA_MASK,
489 .port_ops = &nv_nf2_ops,
477 },
478 /* nforce2/3 */
479 {
480 .sht = &nv_sht,
481 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
482 ATA_FLAG_HRST_TO_RESUME,
483 .pio_mask = NV_PIO_MASK,
484 .mwdma_mask = NV_MWDMA_MASK,
485 .udma_mask = NV_UDMA_MASK,
486 .port_ops = &nv_nf2_ops,
487 .irq_handler = nv_nf2_interrupt,
490 },
491 /* ck804 */
492 {
493 .sht = &nv_sht,
494 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
495 ATA_FLAG_HRST_TO_RESUME,
496 .pio_mask = NV_PIO_MASK,
497 .mwdma_mask = NV_MWDMA_MASK,
498 .udma_mask = NV_UDMA_MASK,
499 .port_ops = &nv_ck804_ops,
488 },
489 /* ck804 */
490 {
491 .sht = &nv_sht,
492 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
493 ATA_FLAG_HRST_TO_RESUME,
494 .pio_mask = NV_PIO_MASK,
495 .mwdma_mask = NV_MWDMA_MASK,
496 .udma_mask = NV_UDMA_MASK,
497 .port_ops = &nv_ck804_ops,
498 .irq_handler = nv_ck804_interrupt,
500 },
501 /* ADMA */
502 {
503 .sht = &nv_adma_sht,
504 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
505 ATA_FLAG_HRST_TO_RESUME |
506 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
507 .pio_mask = NV_PIO_MASK,
508 .mwdma_mask = NV_MWDMA_MASK,
509 .udma_mask = NV_UDMA_MASK,
510 .port_ops = &nv_adma_ops,
499 },
500 /* ADMA */
501 {
502 .sht = &nv_adma_sht,
503 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
504 ATA_FLAG_HRST_TO_RESUME |
505 ATA_FLAG_MMIO | ATA_FLAG_NCQ,
506 .pio_mask = NV_PIO_MASK,
507 .mwdma_mask = NV_MWDMA_MASK,
508 .udma_mask = NV_UDMA_MASK,
509 .port_ops = &nv_adma_ops,
510 .irq_handler = nv_adma_interrupt,
511 },
512};
513
514MODULE_AUTHOR("NVIDIA");
515MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
516MODULE_LICENSE("GPL");
517MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
518MODULE_VERSION(DRV_VERSION);

--- 555 unchanged lines hidden (view full) ---

1074 udelay(1);
1075 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1076 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1077
1078 return 0;
1079}
1080#endif
1081
511 },
512};
513
514MODULE_AUTHOR("NVIDIA");
515MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller");
516MODULE_LICENSE("GPL");
517MODULE_DEVICE_TABLE(pci, nv_pci_tbl);
518MODULE_VERSION(DRV_VERSION);

--- 555 unchanged lines hidden (view full) ---

1074 udelay(1);
1075 writew(tmp & ~NV_ADMA_CTL_CHANNEL_RESET, mmio + NV_ADMA_CTL);
1076 readw( mmio + NV_ADMA_CTL ); /* flush posted write */
1077
1078 return 0;
1079}
1080#endif
1081
1082static void nv_adma_setup_port(struct ata_probe_ent *probe_ent, unsigned int port)
1082static void nv_adma_setup_port(struct ata_port *ap)
1083{
1083{
1084 void __iomem *mmio = probe_ent->iomap[NV_MMIO_BAR];
1085 struct ata_ioports *ioport = &probe_ent->port[port];
1084 void __iomem *mmio = ap->host->iomap[NV_MMIO_BAR];
1085 struct ata_ioports *ioport = &ap->ioaddr;
1086
1087 VPRINTK("ENTER\n");
1088
1086
1087 VPRINTK("ENTER\n");
1088
1089 mmio += NV_ADMA_PORT + port * NV_ADMA_PORT_SIZE;
1089 mmio += NV_ADMA_PORT + ap->port_no * NV_ADMA_PORT_SIZE;
1090
1091 ioport->cmd_addr = mmio;
1092 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
1093 ioport->error_addr =
1094 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1095 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1096 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1097 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1098 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1099 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
1100 ioport->status_addr =
1101 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
1102 ioport->altstatus_addr =
1103 ioport->ctl_addr = mmio + 0x20;
1104}
1105
1090
1091 ioport->cmd_addr = mmio;
1092 ioport->data_addr = mmio + (ATA_REG_DATA * 4);
1093 ioport->error_addr =
1094 ioport->feature_addr = mmio + (ATA_REG_ERR * 4);
1095 ioport->nsect_addr = mmio + (ATA_REG_NSECT * 4);
1096 ioport->lbal_addr = mmio + (ATA_REG_LBAL * 4);
1097 ioport->lbam_addr = mmio + (ATA_REG_LBAM * 4);
1098 ioport->lbah_addr = mmio + (ATA_REG_LBAH * 4);
1099 ioport->device_addr = mmio + (ATA_REG_DEVICE * 4);
1100 ioport->status_addr =
1101 ioport->command_addr = mmio + (ATA_REG_STATUS * 4);
1102 ioport->altstatus_addr =
1103 ioport->ctl_addr = mmio + 0x20;
1104}
1105
1106static int nv_adma_host_init(struct ata_probe_ent *probe_ent)
1106static int nv_adma_host_init(struct ata_host *host)
1107{
1107{
1108 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
1108 struct pci_dev *pdev = to_pci_dev(host->dev);
1109 unsigned int i;
1110 u32 tmp32;
1111
1112 VPRINTK("ENTER\n");
1113
1114 /* enable ADMA on the ports */
1115 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1116 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1117 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1118 NV_MCP_SATA_CFG_20_PORT1_EN |
1119 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1120
1121 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1122
1109 unsigned int i;
1110 u32 tmp32;
1111
1112 VPRINTK("ENTER\n");
1113
1114 /* enable ADMA on the ports */
1115 pci_read_config_dword(pdev, NV_MCP_SATA_CFG_20, &tmp32);
1116 tmp32 |= NV_MCP_SATA_CFG_20_PORT0_EN |
1117 NV_MCP_SATA_CFG_20_PORT0_PWB_EN |
1118 NV_MCP_SATA_CFG_20_PORT1_EN |
1119 NV_MCP_SATA_CFG_20_PORT1_PWB_EN;
1120
1121 pci_write_config_dword(pdev, NV_MCP_SATA_CFG_20, tmp32);
1122
1123 for (i = 0; i < probe_ent->n_ports; i++)
1124 nv_adma_setup_port(probe_ent, i);
1123 for (i = 0; i < host->n_ports; i++)
1124 nv_adma_setup_port(host->ports[i]);
1125
1126 return 0;
1127}
1128
1129static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1130 struct scatterlist *sg,
1131 int idx,
1132 struct nv_adma_prd *aprd)

--- 342 unchanged lines hidden (view full) ---

1475
1476 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1477 nv_hardreset, ata_std_postreset);
1478}
1479
1480static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1481{
1482 static int printed_version = 0;
1125
1126 return 0;
1127}
1128
1129static void nv_adma_fill_aprd(struct ata_queued_cmd *qc,
1130 struct scatterlist *sg,
1131 int idx,
1132 struct nv_adma_prd *aprd)

--- 342 unchanged lines hidden (view full) ---

1475
1476 ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset,
1477 nv_hardreset, ata_std_postreset);
1478}
1479
1480static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
1481{
1482 static int printed_version = 0;
1483 struct ata_port_info *ppi[2];
1484 struct ata_probe_ent *probe_ent;
1483 const struct ata_port_info *ppi[2];
1484 struct ata_host *host;
1485 struct nv_host_priv *hpriv;
1486 int rc;
1487 u32 bar;
1488 void __iomem *base;
1489 unsigned long type = ent->driver_data;
1485 struct nv_host_priv *hpriv;
1486 int rc;
1487 u32 bar;
1488 void __iomem *base;
1489 unsigned long type = ent->driver_data;
1490 int mask_set = 0;
1491
1492 // Make sure this is a SATA controller by counting the number of bars
1493 // (NVIDIA SATA controllers will always have six bars). Otherwise,
1494 // it's an IDE controller and we ignore it.
1495 for (bar=0; bar<6; bar++)
1496 if (pci_resource_start(pdev, bar) == 0)
1497 return -ENODEV;
1498
1499 if (!printed_version++)
1500 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1501
1502 rc = pcim_enable_device(pdev);
1503 if (rc)
1504 return rc;
1505
1490
1491 // Make sure this is a SATA controller by counting the number of bars
1492 // (NVIDIA SATA controllers will always have six bars). Otherwise,
1493 // it's an IDE controller and we ignore it.
1494 for (bar=0; bar<6; bar++)
1495 if (pci_resource_start(pdev, bar) == 0)
1496 return -ENODEV;
1497
1498 if (!printed_version++)
1499 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
1500
1501 rc = pcim_enable_device(pdev);
1502 if (rc)
1503 return rc;
1504
1506 rc = pci_request_regions(pdev, DRV_NAME);
1507 if (rc) {
1508 pcim_pin_device(pdev);
1509 return rc;
1510 }
1511
1512 if(type >= CK804 && adma_enabled) {
1505 /* determine type and allocate host */
1506 if (type >= CK804 && adma_enabled) {
1513 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1514 type = ADMA;
1507 dev_printk(KERN_NOTICE, &pdev->dev, "Using ADMA mode\n");
1508 type = ADMA;
1515 if(!pci_set_dma_mask(pdev, DMA_64BIT_MASK) &&
1516 !pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK))
1517 mask_set = 1;
1518 }
1519
1509 }
1510
1520 if(!mask_set) {
1521 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
1522 if (rc)
1523 return rc;
1524 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
1525 if (rc)
1526 return rc;
1527 }
1511 ppi[0] = ppi[1] = &nv_port_info[type];
1512 rc = ata_pci_prepare_native_host(pdev, ppi, 2, &host);
1513 if (rc)
1514 return rc;
1528
1515
1529 rc = -ENOMEM;
1530
1531 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1532 if (!hpriv)
1533 return -ENOMEM;
1516 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1517 if (!hpriv)
1518 return -ENOMEM;
1519 hpriv->type = type;
1520 host->private_data = hpriv;
1534
1521
1535 ppi[0] = ppi[1] = &nv_port_info[type];
1536 probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY);
1537 if (!probe_ent)
1538 return -ENOMEM;
1522 /* set 64bit dma masks, may fail */
1523 if (type == ADMA) {
1524 if (pci_set_dma_mask(pdev, DMA_64BIT_MASK) == 0)
1525 pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
1526 }
1539
1527
1540 if (!pcim_iomap(pdev, NV_MMIO_BAR, 0))
1541 return -EIO;
1542 probe_ent->iomap = pcim_iomap_table(pdev);
1528 /* request and iomap NV_MMIO_BAR */
1529 rc = pcim_iomap_regions(pdev, 1 << NV_MMIO_BAR, DRV_NAME);
1530 if (rc)
1531 return rc;
1543
1532
1544 probe_ent->private_data = hpriv;
1545 hpriv->type = type;
1533 /* configure SCR access */
1534 base = host->iomap[NV_MMIO_BAR];
1535 host->ports[0]->ioaddr.scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
1536 host->ports[1]->ioaddr.scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1546
1537
1547 base = probe_ent->iomap[NV_MMIO_BAR];
1548 probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET;
1549 probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET;
1550
1551 /* enable SATA space for CK804 */
1552 if (type >= CK804) {
1553 u8 regval;
1554
1555 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1556 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1557 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1558 }
1559
1538 /* enable SATA space for CK804 */
1539 if (type >= CK804) {
1540 u8 regval;
1541
1542 pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, &regval);
1543 regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN;
1544 pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval);
1545 }
1546
1560 pci_set_master(pdev);
1561
1547 /* init ADMA */
1562 if (type == ADMA) {
1548 if (type == ADMA) {
1563 rc = nv_adma_host_init(probe_ent);
1549 rc = nv_adma_host_init(host);
1564 if (rc)
1565 return rc;
1566 }
1567
1550 if (rc)
1551 return rc;
1552 }
1553
1568 rc = ata_device_add(probe_ent);
1569 if (rc != NV_PORTS)
1570 return -ENODEV;
1571
1572 devm_kfree(&pdev->dev, probe_ent);
1573 return 0;
1554 pci_set_master(pdev);
1555 return ata_host_activate(host, pdev->irq, ppi[0]->irq_handler,
1556 IRQF_SHARED, ppi[0]->sht);
1574}
1575
1576static void nv_remove_one (struct pci_dev *pdev)
1577{
1578 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1579 struct nv_host_priv *hpriv = host->private_data;
1580
1581 ata_pci_remove_one(pdev);

--- 95 unchanged lines hidden --- 		1557}
1558
1559static void nv_remove_one (struct pci_dev *pdev)
1560{
1561 struct ata_host *host = dev_get_drvdata(&pdev->dev);
1562 struct nv_host_priv *hpriv = host->private_data;
1563
1564 ata_pci_remove_one(pdev);

--- 95 unchanged lines hidden ---