sata_nv.c (258c9fded4d4024fbe5fae7739d5d159f3f69697) sata_nv.c (4e5b6260cc9ba84ec127f948173ff7d87581f029)
1/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify

--- 1328 unchanged lines hidden (view full) ---

1337 struct nv_adma_prd *aprd;
1338 struct scatterlist *sg;
1339 unsigned int si;
1340
1341 VPRINTK("ENTER\n");
1342
1343 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1344 aprd = (si < 5) ? &cpb->aprd[si] :
1/*
2 * sata_nv.c - NVIDIA nForce SATA
3 *
4 * Copyright 2004 NVIDIA Corp. All rights reserved.
5 * Copyright 2004 Andrew Chew
6 *
7 *
8 * This program is free software; you can redistribute it and/or modify

--- 1328 unchanged lines hidden (view full) ---

1337 struct nv_adma_prd *aprd;
1338 struct scatterlist *sg;
1339 unsigned int si;
1340
1341 VPRINTK("ENTER\n");
1342
1343 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1344 aprd = (si < 5) ? &cpb->aprd[si] :
1345 &pp->aprd[NV_ADMA_SGTBL_LEN * qc->tag + (si-5)];
1345 &pp->aprd[NV_ADMA_SGTBL_LEN * qc->hw_tag + (si-5)];
1346 nv_adma_fill_aprd(qc, sg, si, aprd);
1347 }
1348 if (si > 5)
1346 nv_adma_fill_aprd(qc, sg, si, aprd);
1347 }
1348 if (si > 5)
1349 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->tag)));
1349 cpb->next_aprd = cpu_to_le64(((u64)(pp->aprd_dma + NV_ADMA_SGTBL_SZ * qc->hw_tag)));
1350 else
1351 cpb->next_aprd = cpu_to_le64(0);
1352}
1353
1354static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1355{
1356 struct nv_adma_port_priv *pp = qc->ap->private_data;
1357

--- 8 unchanged lines hidden (view full) ---

1366 return 0;
1367
1368 return 1;
1369}
1370
1371static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1372{
1373 struct nv_adma_port_priv *pp = qc->ap->private_data;
1350 else
1351 cpb->next_aprd = cpu_to_le64(0);
1352}
1353
1354static int nv_adma_use_reg_mode(struct ata_queued_cmd *qc)
1355{
1356 struct nv_adma_port_priv *pp = qc->ap->private_data;
1357

--- 8 unchanged lines hidden (view full) ---

1366 return 0;
1367
1368 return 1;
1369}
1370
1371static void nv_adma_qc_prep(struct ata_queued_cmd *qc)
1372{
1373 struct nv_adma_port_priv *pp = qc->ap->private_data;
1374 struct nv_adma_cpb *cpb = &pp->cpb[qc->tag];
1374 struct nv_adma_cpb *cpb = &pp->cpb[qc->hw_tag];
1375 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
1376 NV_CPB_CTL_IEN;
1377
1378 if (nv_adma_use_reg_mode(qc)) {
1379 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1380 (qc->flags & ATA_QCFLAG_DMAMAP));
1381 nv_adma_register_mode(qc->ap);
1382 ata_bmdma_qc_prep(qc);
1383 return;
1384 }
1385
1386 cpb->resp_flags = NV_CPB_RESP_DONE;
1387 wmb();
1388 cpb->ctl_flags = 0;
1389 wmb();
1390
1391 cpb->len = 3;
1375 u8 ctl_flags = NV_CPB_CTL_CPB_VALID |
1376 NV_CPB_CTL_IEN;
1377
1378 if (nv_adma_use_reg_mode(qc)) {
1379 BUG_ON(!(pp->flags & NV_ADMA_ATAPI_SETUP_COMPLETE) &&
1380 (qc->flags & ATA_QCFLAG_DMAMAP));
1381 nv_adma_register_mode(qc->ap);
1382 ata_bmdma_qc_prep(qc);
1383 return;
1384 }
1385
1386 cpb->resp_flags = NV_CPB_RESP_DONE;
1387 wmb();
1388 cpb->ctl_flags = 0;
1389 wmb();
1390
1391 cpb->len = 3;
1392 cpb->tag = qc->tag;
1392 cpb->tag = qc->hw_tag;
1393 cpb->next_cpb_idx = 0;
1394
1395 /* turn on NCQ flags for NCQ commands */
1396 if (qc->tf.protocol == ATA_PROT_NCQ)
1397 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1398
1399 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1400

--- 46 unchanged lines hidden (view full) ---

1447
1448 if (curr_ncq != pp->last_issue_ncq) {
1449 /* Seems to need some delay before switching between NCQ and
1450 non-NCQ commands, else we get command timeouts and such. */
1451 udelay(20);
1452 pp->last_issue_ncq = curr_ncq;
1453 }
1454
1393 cpb->next_cpb_idx = 0;
1394
1395 /* turn on NCQ flags for NCQ commands */
1396 if (qc->tf.protocol == ATA_PROT_NCQ)
1397 ctl_flags |= NV_CPB_CTL_QUEUE | NV_CPB_CTL_FPDMA;
1398
1399 VPRINTK("qc->flags = 0x%lx\n", qc->flags);
1400

--- 46 unchanged lines hidden (view full) ---

1447
1448 if (curr_ncq != pp->last_issue_ncq) {
1449 /* Seems to need some delay before switching between NCQ and
1450 non-NCQ commands, else we get command timeouts and such. */
1451 udelay(20);
1452 pp->last_issue_ncq = curr_ncq;
1453 }
1454
1455 writew(qc->tag, mmio + NV_ADMA_APPEND);
1455 writew(qc->hw_tag, mmio + NV_ADMA_APPEND);
1456
1456
1457 DPRINTK("Issued tag %u\n", qc->tag);
1457 DPRINTK("Issued tag %u\n", qc->hw_tag);
1458
1459 return 0;
1460}
1461
1462static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
1463{
1464 struct ata_host *host = dev_instance;
1465 unsigned int i;

--- 245 unchanged lines hidden (view full) ---

1711
1712static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc)
1713{
1714 struct nv_swncq_port_priv *pp = ap->private_data;
1715 struct defer_queue *dq = &pp->defer_queue;
1716
1717 /* queue is full */
1718 WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE);
1458
1459 return 0;
1460}
1461
1462static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance)
1463{
1464 struct ata_host *host = dev_instance;
1465 unsigned int i;

--- 245 unchanged lines hidden (view full) ---

1711
1712static void nv_swncq_qc_to_dq(struct ata_port *ap, struct ata_queued_cmd *qc)
1713{
1714 struct nv_swncq_port_priv *pp = ap->private_data;
1715 struct defer_queue *dq = &pp->defer_queue;
1716
1717 /* queue is full */
1718 WARN_ON(dq->tail - dq->head == ATA_MAX_QUEUE);
1719 dq->defer_bits |= (1 << qc->tag);
1720 dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->tag;
1719 dq->defer_bits |= (1 << qc->hw_tag);
1720 dq->tag[dq->tail++ & (ATA_MAX_QUEUE - 1)] = qc->hw_tag;
1721}
1722
1723static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap)
1724{
1725 struct nv_swncq_port_priv *pp = ap->private_data;
1726 struct defer_queue *dq = &pp->defer_queue;
1727 unsigned int tag;
1728

--- 262 unchanged lines hidden (view full) ---

1991static void nv_swncq_fill_sg(struct ata_queued_cmd *qc)
1992{
1993 struct ata_port *ap = qc->ap;
1994 struct scatterlist *sg;
1995 struct nv_swncq_port_priv *pp = ap->private_data;
1996 struct ata_bmdma_prd *prd;
1997 unsigned int si, idx;
1998
1721}
1722
1723static struct ata_queued_cmd *nv_swncq_qc_from_dq(struct ata_port *ap)
1724{
1725 struct nv_swncq_port_priv *pp = ap->private_data;
1726 struct defer_queue *dq = &pp->defer_queue;
1727 unsigned int tag;
1728

--- 262 unchanged lines hidden (view full) ---

1991static void nv_swncq_fill_sg(struct ata_queued_cmd *qc)
1992{
1993 struct ata_port *ap = qc->ap;
1994 struct scatterlist *sg;
1995 struct nv_swncq_port_priv *pp = ap->private_data;
1996 struct ata_bmdma_prd *prd;
1997 unsigned int si, idx;
1998
1999 prd = pp->prd + ATA_MAX_PRD * qc->tag;
1999 prd = pp->prd + ATA_MAX_PRD * qc->hw_tag;
2000
2001 idx = 0;
2002 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2003 u32 addr, offset;
2004 u32 sg_len, len;
2005
2006 addr = (u32)sg_dma_address(sg);
2007 sg_len = sg_dma_len(sg);

--- 21 unchanged lines hidden (view full) ---

2029{
2030 struct nv_swncq_port_priv *pp = ap->private_data;
2031
2032 if (qc == NULL)
2033 return 0;
2034
2035 DPRINTK("Enter\n");
2036
2000
2001 idx = 0;
2002 for_each_sg(qc->sg, sg, qc->n_elem, si) {
2003 u32 addr, offset;
2004 u32 sg_len, len;
2005
2006 addr = (u32)sg_dma_address(sg);
2007 sg_len = sg_dma_len(sg);

--- 21 unchanged lines hidden (view full) ---

2029{
2030 struct nv_swncq_port_priv *pp = ap->private_data;
2031
2032 if (qc == NULL)
2033 return 0;
2034
2035 DPRINTK("Enter\n");
2036
2037 writel((1 << qc->tag), pp->sactive_block);
2038 pp->last_issue_tag = qc->tag;
2039 pp->dhfis_bits &= ~(1 << qc->tag);
2040 pp->dmafis_bits &= ~(1 << qc->tag);
2041 pp->qc_active |= (0x1 << qc->tag);
2037 writel((1 << qc->hw_tag), pp->sactive_block);
2038 pp->last_issue_tag = qc->hw_tag;
2039 pp->dhfis_bits &= ~(1 << qc->hw_tag);
2040 pp->dmafis_bits &= ~(1 << qc->hw_tag);
2041 pp->qc_active |= (0x1 << qc->hw_tag);
2042
2043 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2044 ap->ops->sff_exec_command(ap, &qc->tf);
2045
2042
2043 ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */
2044 ap->ops->sff_exec_command(ap, &qc->tf);
2045
2046 DPRINTK("Issued tag %u\n", qc->tag);
2046 DPRINTK("Issued tag %u\n", qc->hw_tag);
2047
2048 return 0;
2049}
2050
2051static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc)
2052{
2053 struct ata_port *ap = qc->ap;
2054 struct nv_swncq_port_priv *pp = ap->private_data;

--- 133 unchanged lines hidden (view full) ---

2188 qc = ata_qc_from_tag(ap, tag);
2189
2190 if (unlikely(!qc))
2191 return;
2192
2193 rw = qc->tf.flags & ATA_TFLAG_WRITE;
2194
2195 /* load PRD table addr. */
2047
2048 return 0;
2049}
2050
2051static unsigned int nv_swncq_qc_issue(struct ata_queued_cmd *qc)
2052{
2053 struct ata_port *ap = qc->ap;
2054 struct nv_swncq_port_priv *pp = ap->private_data;

--- 133 unchanged lines hidden (view full) ---

2188 qc = ata_qc_from_tag(ap, tag);
2189
2190 if (unlikely(!qc))
2191 return;
2192
2193 rw = qc->tf.flags & ATA_TFLAG_WRITE;
2194
2195 /* load PRD table addr. */
2196 iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->tag,
2196 iowrite32(pp->prd_dma + ATA_PRD_TBL_SZ * qc->hw_tag,
2197 ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2198
2199 /* specify data direction, triple-check start bit is clear */
2200 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2201 dmactl &= ~ATA_DMA_WR;
2202 if (!rw)
2203 dmactl |= ATA_DMA_WR;
2204

--- 301 unchanged lines hidden --- 		2197 ap->ioaddr.bmdma_addr + ATA_DMA_TABLE_OFS);
2198
2199 /* specify data direction, triple-check start bit is clear */
2200 dmactl = ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
2201 dmactl &= ~ATA_DMA_WR;
2202 if (!rw)
2203 dmactl |= ATA_DMA_WR;
2204

--- 301 unchanged lines hidden ---