sata_mv.c (9dcffd99d0b1c0c1b8b2c0f85d240e791eca1055) sata_mv.c (e40060772d85f3534d3d517197696e24bb01f45b)
1/*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.

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881 if (hc_irq_cause & ipending) {
882 writelfl(hc_irq_cause & ~ipending,
883 hc_mmio + HC_IRQ_CAUSE_OFS);
884 }
885
886 mv_edma_cfg(ap, want_ncq);
887
888 /* clear FIS IRQ Cause */
1/*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.

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881 if (hc_irq_cause & ipending) {
882 writelfl(hc_irq_cause & ~ipending,
883 hc_mmio + HC_IRQ_CAUSE_OFS);
884 }
885
886 mv_edma_cfg(ap, want_ncq);
887
888 /* clear FIS IRQ Cause */
889 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
889 if (IS_GEN_IIE(hpriv))
890 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
890
891 mv_set_edma_ptrs(port_mmio, hpriv, pp);
892
893 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
894 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
895 }
896}
897

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1807 *
1808 * LOCKING:
1809 * Inherited from caller.
1810 */
1811static void mv_err_intr(struct ata_port *ap)
1812{
1813 void __iomem *port_mmio = mv_ap_base(ap);
1814 u32 edma_err_cause, eh_freeze_mask, serr = 0;
891
892 mv_set_edma_ptrs(port_mmio, hpriv, pp);
893
894 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
895 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
896 }
897}
898

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1808 *
1809 * LOCKING:
1810 * Inherited from caller.
1811 */
1812static void mv_err_intr(struct ata_port *ap)
1813{
1814 void __iomem *port_mmio = mv_ap_base(ap);
1815 u32 edma_err_cause, eh_freeze_mask, serr = 0;
1816 u32 fis_cause = 0;
1815 struct mv_port_priv *pp = ap->private_data;
1816 struct mv_host_priv *hpriv = ap->host->private_data;
1817 unsigned int action = 0, err_mask = 0;
1818 struct ata_eh_info *ehi = &ap->link.eh_info;
1819 struct ata_queued_cmd *qc;
1820 int abort = 0;
1821
1822 /*
1823 * Read and clear the SError and err_cause bits.
1817 struct mv_port_priv *pp = ap->private_data;
1818 struct mv_host_priv *hpriv = ap->host->private_data;
1819 unsigned int action = 0, err_mask = 0;
1820 struct ata_eh_info *ehi = &ap->link.eh_info;
1821 struct ata_queued_cmd *qc;
1822 int abort = 0;
1823
1824 /*
1825 * Read and clear the SError and err_cause bits.
1826 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1827 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
1824 */
1825 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1826 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1827
1828 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1828 */
1829 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1830 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1831
1832 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1833 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1834 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1835 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1836 }
1829 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1830
1837 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
1838
1831 ata_port_printk(ap, KERN_INFO, "%s: err_cause=%08x pp_flags=0x%x\n",
1832 __func__, edma_err_cause, pp->pp_flags);
1833
1834 if (edma_err_cause & EDMA_ERR_DEV) {
1835 /*
1836 * Device errors during FIS-based switching operation
1837 * require special handling.
1838 */
1839 if (mv_handle_dev_err(ap, edma_err_cause))
1840 return;
1841 }
1842
1843 qc = mv_get_active_qc(ap);
1844 ata_ehi_clear_desc(ehi);
1845 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1846 edma_err_cause, pp->pp_flags);
1839 if (edma_err_cause & EDMA_ERR_DEV) {
1840 /*
1841 * Device errors during FIS-based switching operation
1842 * require special handling.
1843 */
1844 if (mv_handle_dev_err(ap, edma_err_cause))
1845 return;
1846 }
1847
1848 qc = mv_get_active_qc(ap);
1849 ata_ehi_clear_desc(ehi);
1850 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1851 edma_err_cause, pp->pp_flags);
1852
1853 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7))
1854 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
1847 /*
1848 * All generations share these EDMA error cause bits:
1849 */
1850 if (edma_err_cause & EDMA_ERR_DEV) {
1851 err_mask |= AC_ERR_DEV;
1852 action |= ATA_EH_RESET;
1853 ata_ehi_push_desc(ehi, "dev error");
1854 }

--- 1607 unchanged lines hidden --- 		1855 /*
1856 * All generations share these EDMA error cause bits:
1857 */
1858 if (edma_err_cause & EDMA_ERR_DEV) {
1859 err_mask |= AC_ERR_DEV;
1860 action |= ATA_EH_RESET;
1861 ata_ehi_push_desc(ehi, "dev error");
1862 }

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