sata_mv.c (552c69b36ebd966186573b9c7a286b390935cce1) sata_mv.c (4e5b6260cc9ba84ec127f948173ff7d87581f029)
1/*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Originally written by Brett Russ.

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1797 */
1798static void mv_fill_sg(struct ata_queued_cmd *qc)
1799{
1800 struct mv_port_priv *pp = qc->ap->private_data;
1801 struct scatterlist *sg;
1802 struct mv_sg *mv_sg, *last_sg = NULL;
1803 unsigned int si;
1804
1/*
2 * sata_mv.c - Marvell SATA support
3 *
4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
5 * Copyright 2005: EMC Corporation, all rights reserved.
6 * Copyright 2005 Red Hat, Inc. All rights reserved.
7 *
8 * Originally written by Brett Russ.

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1797 */
1798static void mv_fill_sg(struct ata_queued_cmd *qc)
1799{
1800 struct mv_port_priv *pp = qc->ap->private_data;
1801 struct scatterlist *sg;
1802 struct mv_sg *mv_sg, *last_sg = NULL;
1803 unsigned int si;
1804
1805 mv_sg = pp->sg_tbl[qc->tag];
1805 mv_sg = pp->sg_tbl[qc->hw_tag];
1806 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1807 dma_addr_t addr = sg_dma_address(sg);
1808 u32 sg_len = sg_dma_len(sg);
1809
1810 while (sg_len) {
1811 u32 offset = addr & 0xffff;
1812 u32 len = sg_len;
1813

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1898 struct mv_port_priv *pp = ap->private_data;
1899
1900 mv_fill_sg(qc);
1901
1902 /* clear all DMA cmd bits */
1903 writel(0, port_mmio + BMDMA_CMD);
1904
1905 /* load PRD table addr. */
1806 for_each_sg(qc->sg, sg, qc->n_elem, si) {
1807 dma_addr_t addr = sg_dma_address(sg);
1808 u32 sg_len = sg_dma_len(sg);
1809
1810 while (sg_len) {
1811 u32 offset = addr & 0xffff;
1812 u32 len = sg_len;
1813

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1898 struct mv_port_priv *pp = ap->private_data;
1899
1900 mv_fill_sg(qc);
1901
1902 /* clear all DMA cmd bits */
1903 writel(0, port_mmio + BMDMA_CMD);
1904
1905 /* load PRD table addr. */
1906 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1906 writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16,
1907 port_mmio + BMDMA_PRD_HIGH);
1907 port_mmio + BMDMA_PRD_HIGH);
1908 writelfl(pp->sg_tbl_dma[qc->tag],
1908 writelfl(pp->sg_tbl_dma[qc->hw_tag],
1909 port_mmio + BMDMA_PRD_LOW);
1910
1911 /* issue r/w command */
1912 ap->ops->sff_exec_command(ap, &qc->tf);
1913}
1914
1915/**
1916 * mv_bmdma_start - Start a BMDMA transaction

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2066 default:
2067 return;
2068 }
2069
2070 /* Fill in command request block
2071 */
2072 if (!(tf->flags & ATA_TFLAG_WRITE))
2073 flags |= CRQB_FLAG_READ;
1909 port_mmio + BMDMA_PRD_LOW);
1910
1911 /* issue r/w command */
1912 ap->ops->sff_exec_command(ap, &qc->tf);
1913}
1914
1915/**
1916 * mv_bmdma_start - Start a BMDMA transaction

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2066 default:
2067 return;
2068 }
2069
2070 /* Fill in command request block
2071 */
2072 if (!(tf->flags & ATA_TFLAG_WRITE))
2073 flags |= CRQB_FLAG_READ;
2074 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2075 flags |= qc->tag << CRQB_TAG_SHIFT;
2074 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag);
2075 flags |= qc->hw_tag << CRQB_TAG_SHIFT;
2076 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2077
2078 /* get current queue index from software */
2079 in_index = pp->req_idx;
2080
2081 pp->crqb[in_index].sg_addr =
2076 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2077
2078 /* get current queue index from software */
2079 in_index = pp->req_idx;
2080
2081 pp->crqb[in_index].sg_addr =
2082 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2082 cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff);
2083 pp->crqb[in_index].sg_addr_hi =
2083 pp->crqb[in_index].sg_addr_hi =
2084 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2084 cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16);
2085 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2086
2087 cw = &pp->crqb[in_index].ata_cmd[0];
2088
2089 /* Sadly, the CRQB cannot accommodate all registers--there are
2090 * only 11 bytes...so we must pick and choose required
2091 * registers based on the command. So, we drop feature and
2092 * hob_feature for [RW] DMA commands, but they are needed for

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2159 return;
2160 if (tf->command == ATA_CMD_DSM)
2161 return; /* use bmdma for this */
2162
2163 /* Fill in Gen IIE command request block */
2164 if (!(tf->flags & ATA_TFLAG_WRITE))
2165 flags |= CRQB_FLAG_READ;
2166
2085 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
2086
2087 cw = &pp->crqb[in_index].ata_cmd[0];
2088
2089 /* Sadly, the CRQB cannot accommodate all registers--there are
2090 * only 11 bytes...so we must pick and choose required
2091 * registers based on the command. So, we drop feature and
2092 * hob_feature for [RW] DMA commands, but they are needed for

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2159 return;
2160 if (tf->command == ATA_CMD_DSM)
2161 return; /* use bmdma for this */
2162
2163 /* Fill in Gen IIE command request block */
2164 if (!(tf->flags & ATA_TFLAG_WRITE))
2165 flags |= CRQB_FLAG_READ;
2166
2167 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
2168 flags |= qc->tag << CRQB_TAG_SHIFT;
2169 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
2167 WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag);
2168 flags |= qc->hw_tag << CRQB_TAG_SHIFT;
2169 flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT;
2170 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2171
2172 /* get current queue index from software */
2173 in_index = pp->req_idx;
2174
2175 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2170 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
2171
2172 /* get current queue index from software */
2173 in_index = pp->req_idx;
2174
2175 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
2176 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2177 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
2176 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff);
2177 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16);
2178 crqb->flags = cpu_to_le32(flags);
2179
2180 crqb->ata_cmd[0] = cpu_to_le32(
2181 (tf->command << 16) |
2182 (tf->feature << 24)
2183 );
2184 crqb->ata_cmd[1] = cpu_to_le32(
2185 (tf->lbal << 0) |

--- 2351 unchanged lines hidden --- 		2178 crqb->flags = cpu_to_le32(flags);
2179
2180 crqb->ata_cmd[0] = cpu_to_le32(
2181 (tf->command << 16) |
2182 (tf->feature << 24)
2183 );
2184 crqb->ata_cmd[1] = cpu_to_le32(
2185 (tf->lbal << 0) |

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