sata_inic162x.c (f8b0685a8ea8e3974f8953378ede2111f8d49d22) sata_inic162x.c (ba66b242b1c3432b44d893c64124522b3bdce71e)
1/*
2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
3 *
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
6 *
7 * This file is released under GPL v2.
8 *

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26#include <linux/libata.h>
27#include <linux/blkdev.h>
28#include <scsi/scsi_device.h>
29
30#define DRV_NAME "sata_inic162x"
31#define DRV_VERSION "0.3"
32
33enum {
1/*
2 * sata_inic162x.c - Driver for Initio 162x SATA controllers
3 *
4 * Copyright 2006 SUSE Linux Products GmbH
5 * Copyright 2006 Tejun Heo <teheo@novell.com>
6 *
7 * This file is released under GPL v2.
8 *

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26#include <linux/libata.h>
27#include <linux/blkdev.h>
28#include <scsi/scsi_device.h>
29
30#define DRV_NAME "sata_inic162x"
31#define DRV_VERSION "0.3"
32
33enum {
34 MMIO_BAR = 5,
34 MMIO_BAR_PCI = 5,
35 MMIO_BAR_CARDBUS = 1,
35
36 NR_PORTS = 2,
37
38 IDMA_CPB_TBL_SIZE = 4 * 32,
39
40 INIC_DMA_BOUNDARY = 0xffffff,
41
42 HOST_ACTRL = 0x08,

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192
193struct inic_pkt {
194 struct inic_cpb cpb;
195 struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
196 u8 cdb[ATAPI_CDB_LEN];
197} __packed;
198
199struct inic_host_priv {
36
37 NR_PORTS = 2,
38
39 IDMA_CPB_TBL_SIZE = 4 * 32,
40
41 INIC_DMA_BOUNDARY = 0xffffff,
42
43 HOST_ACTRL = 0x08,

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193
194struct inic_pkt {
195 struct inic_cpb cpb;
196 struct inic_prd prd[LIBATA_MAX_PRD + 1]; /* + 1 for cdb */
197 u8 cdb[ATAPI_CDB_LEN];
198} __packed;
199
200struct inic_host_priv {
201 void __iomem *mmio_base;
200 u16 cached_hctl;
201};
202
203struct inic_port_priv {
204 struct inic_pkt *pkt;
205 dma_addr_t pkt_dma;
206 u32 *cpb_tbl;
207 dma_addr_t cpb_tbl_dma;

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216static const int scr_map[] = {
217 [SCR_STATUS] = 0,
218 [SCR_ERROR] = 1,
219 [SCR_CONTROL] = 2,
220};
221
222static void __iomem *inic_port_base(struct ata_port *ap)
223{
202 u16 cached_hctl;
203};
204
205struct inic_port_priv {
206 struct inic_pkt *pkt;
207 dma_addr_t pkt_dma;
208 u32 *cpb_tbl;
209 dma_addr_t cpb_tbl_dma;

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218static const int scr_map[] = {
219 [SCR_STATUS] = 0,
220 [SCR_ERROR] = 1,
221 [SCR_CONTROL] = 2,
222};
223
224static void __iomem *inic_port_base(struct ata_port *ap)
225{
224 return ap->host->iomap[MMIO_BAR] + ap->port_no * PORT_SIZE;
226 struct inic_host_priv *hpriv = ap->host->private_data;
227
228 return hpriv->mmio_base + ap->port_no * PORT_SIZE;
225}
226
227static void inic_reset_port(void __iomem *port_base)
228{
229 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
230
231 /* stop IDMA engine */
232 readw(idma_ctl); /* flush */

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373 ata_port_printk(ap, KERN_WARNING, "unhandled interrupt: "
374 "cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
375 qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
376}
377
378static irqreturn_t inic_interrupt(int irq, void *dev_instance)
379{
380 struct ata_host *host = dev_instance;
229}
230
231static void inic_reset_port(void __iomem *port_base)
232{
233 void __iomem *idma_ctl = port_base + PORT_IDMA_CTL;
234
235 /* stop IDMA engine */
236 readw(idma_ctl); /* flush */

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377 ata_port_printk(ap, KERN_WARNING, "unhandled interrupt: "
378 "cmd=0x%x irq_stat=0x%x idma_stat=0x%x\n",
379 qc ? qc->tf.command : 0xff, irq_stat, idma_stat);
380}
381
382static irqreturn_t inic_interrupt(int irq, void *dev_instance)
383{
384 struct ata_host *host = dev_instance;
381 void __iomem *mmio_base = host->iomap[MMIO_BAR];
385 struct inic_host_priv *hpriv = host->private_data;
382 u16 host_irq_stat;
383 int i, handled = 0;;
384
386 u16 host_irq_stat;
387 int i, handled = 0;;
388
385 host_irq_stat = readw(mmio_base + HOST_IRQ_STAT);
389 host_irq_stat = readw(hpriv->mmio_base + HOST_IRQ_STAT);
386
387 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
388 goto out;
389
390 spin_lock(&host->lock);
391
392 for (i = 0; i < NR_PORTS; i++) {
393 struct ata_port *ap = host->ports[i];

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765 return 0;
766}
767
768#ifdef CONFIG_PM
769static int inic_pci_device_resume(struct pci_dev *pdev)
770{
771 struct ata_host *host = dev_get_drvdata(&pdev->dev);
772 struct inic_host_priv *hpriv = host->private_data;
390
391 if (unlikely(!(host_irq_stat & HIRQ_GLOBAL)))
392 goto out;
393
394 spin_lock(&host->lock);
395
396 for (i = 0; i < NR_PORTS; i++) {
397 struct ata_port *ap = host->ports[i];

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769 return 0;
770}
771
772#ifdef CONFIG_PM
773static int inic_pci_device_resume(struct pci_dev *pdev)
774{
775 struct ata_host *host = dev_get_drvdata(&pdev->dev);
776 struct inic_host_priv *hpriv = host->private_data;
773 void __iomem *mmio_base = host->iomap[MMIO_BAR];
774 int rc;
775
776 rc = ata_pci_device_do_resume(pdev);
777 if (rc)
778 return rc;
779
780 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
777 int rc;
778
779 rc = ata_pci_device_do_resume(pdev);
780 if (rc)
781 return rc;
782
783 if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) {
781 rc = init_controller(mmio_base, hpriv->cached_hctl);
784 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
782 if (rc)
783 return rc;
784 }
785
786 ata_host_resume(host);
787
788 return 0;
789}
790#endif
791
792static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
793{
794 static int printed_version;
795 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
796 struct ata_host *host;
797 struct inic_host_priv *hpriv;
798 void __iomem * const *iomap;
785 if (rc)
786 return rc;
787 }
788
789 ata_host_resume(host);
790
791 return 0;
792}
793#endif
794
795static int inic_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
796{
797 static int printed_version;
798 const struct ata_port_info *ppi[] = { &inic_port_info, NULL };
799 struct ata_host *host;
800 struct inic_host_priv *hpriv;
801 void __iomem * const *iomap;
802 int mmio_bar;
799 int i, rc;
800
801 if (!printed_version++)
802 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
803
804 /* alloc host */
805 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
806 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
807 if (!host || !hpriv)
808 return -ENOMEM;
809
810 host->private_data = hpriv;
811
803 int i, rc;
804
805 if (!printed_version++)
806 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
807
808 /* alloc host */
809 host = ata_host_alloc_pinfo(&pdev->dev, ppi, NR_PORTS);
810 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
811 if (!host || !hpriv)
812 return -ENOMEM;
813
814 host->private_data = hpriv;
815
812 /* acquire resources and fill host */
816 /* Acquire resources and fill host. Note that PCI and cardbus
817 * use different BARs.
818 */
813 rc = pcim_enable_device(pdev);
814 if (rc)
815 return rc;
816
819 rc = pcim_enable_device(pdev);
820 if (rc)
821 return rc;
822
817 rc = pcim_iomap_regions(pdev, 1 << MMIO_BAR, DRV_NAME);
823 if (pci_resource_flags(pdev, MMIO_BAR_PCI) & IORESOURCE_MEM)
824 mmio_bar = MMIO_BAR_PCI;
825 else
826 mmio_bar = MMIO_BAR_CARDBUS;
827
828 rc = pcim_iomap_regions(pdev, 1 << mmio_bar, DRV_NAME);
818 if (rc)
819 return rc;
820 host->iomap = iomap = pcim_iomap_table(pdev);
829 if (rc)
830 return rc;
831 host->iomap = iomap = pcim_iomap_table(pdev);
821 hpriv->cached_hctl = readw(iomap[MMIO_BAR] + HOST_CTL);
832 hpriv->mmio_base = iomap[mmio_bar];
833 hpriv->cached_hctl = readw(hpriv->mmio_base + HOST_CTL);
822
823 for (i = 0; i < NR_PORTS; i++) {
824 struct ata_port *ap = host->ports[i];
825
834
835 for (i = 0; i < NR_PORTS; i++) {
836 struct ata_port *ap = host->ports[i];
837
826 ata_port_pbar_desc(ap, MMIO_BAR, -1, "mmio");
827 ata_port_pbar_desc(ap, MMIO_BAR, i * PORT_SIZE, "port");
838 ata_port_pbar_desc(ap, mmio_bar, -1, "mmio");
839 ata_port_pbar_desc(ap, mmio_bar, i * PORT_SIZE, "port");
828 }
829
830 /* Set dma_mask. This devices doesn't support 64bit addressing. */
831 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
832 if (rc) {
833 dev_printk(KERN_ERR, &pdev->dev,
834 "32-bit DMA enable failed\n");
835 return rc;

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849 */
850 rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
851 if (rc) {
852 dev_printk(KERN_ERR, &pdev->dev,
853 "failed to set the maximum segment size.\n");
854 return rc;
855 }
856
840 }
841
842 /* Set dma_mask. This devices doesn't support 64bit addressing. */
843 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
844 if (rc) {
845 dev_printk(KERN_ERR, &pdev->dev,
846 "32-bit DMA enable failed\n");
847 return rc;

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861 */
862 rc = pci_set_dma_max_seg_size(pdev, 65536 - 512);
863 if (rc) {
864 dev_printk(KERN_ERR, &pdev->dev,
865 "failed to set the maximum segment size.\n");
866 return rc;
867 }
868
857 rc = init_controller(iomap[MMIO_BAR], hpriv->cached_hctl);
869 rc = init_controller(hpriv->mmio_base, hpriv->cached_hctl);
858 if (rc) {
859 dev_printk(KERN_ERR, &pdev->dev,
860 "failed to initialize controller\n");
861 return rc;
862 }
863
864 pci_set_master(pdev);
865 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,

--- 37 unchanged lines hidden --- 		870 if (rc) {
871 dev_printk(KERN_ERR, &pdev->dev,
872 "failed to initialize controller\n");
873 return rc;
874 }
875
876 pci_set_master(pdev);
877 return ata_host_activate(host, pdev->irq, inic_interrupt, IRQF_SHARED,

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