sata_fsl.c (1aadf5c3bbbbb0db09dcb5aa26c61326e0d3e9e7) sata_fsl.c (97750cebb3000a9cc08f8ce8dc8c7143be7d7201)
1/*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *

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673 * Force host controller to go off-line, aborting current operations
674 */
675 temp = ioread32(hcr_base + HCONTROL);
676 temp &= ~HCONTROL_ONLINE_PHY_RST;
677 temp |= HCONTROL_FORCE_OFFLINE;
678 iowrite32(temp, hcr_base + HCONTROL);
679
680 /* Poll for controller to go offline - should happen immediately */
1/*
2 * drivers/ata/sata_fsl.c
3 *
4 * Freescale 3.0Gbps SATA device driver
5 *
6 * Author: Ashish Kalra <ashish.kalra@freescale.com>
7 * Li Yang <leoli@freescale.com>
8 *

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673 * Force host controller to go off-line, aborting current operations
674 */
675 temp = ioread32(hcr_base + HCONTROL);
676 temp &= ~HCONTROL_ONLINE_PHY_RST;
677 temp |= HCONTROL_FORCE_OFFLINE;
678 iowrite32(temp, hcr_base + HCONTROL);
679
680 /* Poll for controller to go offline - should happen immediately */
681 ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
681 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
682
683 ap->private_data = NULL;
684 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
685 pp->cmdslot, pp->cmdslot_paddr);
686
687 kfree(pp);
688}
689

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724 /*
725 * Force host controller to go off-line, aborting current operations
726 */
727 temp = ioread32(hcr_base + HCONTROL);
728 temp &= ~HCONTROL_ONLINE_PHY_RST;
729 iowrite32(temp, hcr_base + HCONTROL);
730
731 /* Poll for controller to go offline */
682
683 ap->private_data = NULL;
684 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
685 pp->cmdslot, pp->cmdslot_paddr);
686
687 kfree(pp);
688}
689

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724 /*
725 * Force host controller to go off-line, aborting current operations
726 */
727 temp = ioread32(hcr_base + HCONTROL);
728 temp &= ~HCONTROL_ONLINE_PHY_RST;
729 iowrite32(temp, hcr_base + HCONTROL);
730
731 /* Poll for controller to go offline */
732 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, ONLINE, 1, 500);
732 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
733 1, 500);
733
734 if (temp & ONLINE) {
735 ata_port_printk(ap, KERN_ERR,
736 "Hardreset failed, not off-lined %d\n", i);
737
738 /*
739 * Try to offline controller atleast twice
740 */

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747
748 DPRINTK("hardreset, controller off-lined\n");
749 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
750 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
751
752 /*
753 * PHY reset should remain asserted for atleast 1ms
754 */
734
735 if (temp & ONLINE) {
736 ata_port_printk(ap, KERN_ERR,
737 "Hardreset failed, not off-lined %d\n", i);
738
739 /*
740 * Try to offline controller atleast twice
741 */

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748
749 DPRINTK("hardreset, controller off-lined\n");
750 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
751 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
752
753 /*
754 * PHY reset should remain asserted for atleast 1ms
755 */
755 msleep(1);
756 ata_msleep(ap, 1);
756
757 /*
758 * Now, bring the host controller online again, this can take time
759 * as PHY reset and communication establishment, 1st D2H FIS and
760 * device signature update is done, on safe side assume 500ms
761 * NOTE : Host online status may be indicated immediately!!
762 */
763
764 temp = ioread32(hcr_base + HCONTROL);
765 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
766 temp |= HCONTROL_PMP_ATTACHED;
767 iowrite32(temp, hcr_base + HCONTROL);
768
757
758 /*
759 * Now, bring the host controller online again, this can take time
760 * as PHY reset and communication establishment, 1st D2H FIS and
761 * device signature update is done, on safe side assume 500ms
762 * NOTE : Host online status may be indicated immediately!!
763 */
764
765 temp = ioread32(hcr_base + HCONTROL);
766 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
767 temp |= HCONTROL_PMP_ATTACHED;
768 iowrite32(temp, hcr_base + HCONTROL);
769
769 temp = ata_wait_register(hcr_base + HSTATUS, ONLINE, 0, 1, 500);
770 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
770
771 if (!(temp & ONLINE)) {
772 ata_port_printk(ap, KERN_ERR,
773 "Hardreset failed, not on-lined\n");
774 goto err;
775 }
776
777 DPRINTK("hardreset, controller off-lined & on-lined\n");
778 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
779 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
780
781 /*
782 * First, wait for the PHYRDY change to occur before waiting for
783 * the signature, and also verify if SStatus indicates device
784 * presence
785 */
786
771
772 if (!(temp & ONLINE)) {
773 ata_port_printk(ap, KERN_ERR,
774 "Hardreset failed, not on-lined\n");
775 goto err;
776 }
777
778 DPRINTK("hardreset, controller off-lined & on-lined\n");
779 VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
780 VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
781
782 /*
783 * First, wait for the PHYRDY change to occur before waiting for
784 * the signature, and also verify if SStatus indicates device
785 * presence
786 */
787
787 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0, 1, 500);
788 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
788 if ((!(temp & 0x10)) || ata_link_offline(link)) {
789 ata_port_printk(ap, KERN_WARNING,
790 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
791 ioread32(hcr_base + HSTATUS));
792 *class = ATA_DEV_NONE;
793 return 0;
794 }
795
796 /*
797 * Wait for the first D2H from device,i.e,signature update notification
798 */
799 start_jiffies = jiffies;
789 if ((!(temp & 0x10)) || ata_link_offline(link)) {
790 ata_port_printk(ap, KERN_WARNING,
791 "No Device OR PHYRDY change,Hstatus = 0x%x\n",
792 ioread32(hcr_base + HSTATUS));
793 *class = ATA_DEV_NONE;
794 return 0;
795 }
796
797 /*
798 * Wait for the first D2H from device,i.e,signature update notification
799 */
800 start_jiffies = jiffies;
800 temp = ata_wait_register(hcr_base + HSTATUS, 0xFF, 0x10,
801 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
801 500, jiffies_to_msecs(deadline - start_jiffies));
802
803 if ((temp & 0xFF) != 0x18) {
804 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
805 *class = ATA_DEV_NONE;
806 goto do_followup_srst;
807 } else {
808 ata_port_printk(ap, KERN_INFO,

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875 ioread32(CQ + hcr_base),
876 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
877
878 iowrite32(0xFFFF, CC + hcr_base);
879 if (pmp != SATA_PMP_CTRL_PORT)
880 iowrite32(pmp, CQPMP + hcr_base);
881 iowrite32(1, CQ + hcr_base);
882
802 500, jiffies_to_msecs(deadline - start_jiffies));
803
804 if ((temp & 0xFF) != 0x18) {
805 ata_port_printk(ap, KERN_WARNING, "No Signature Update\n");
806 *class = ATA_DEV_NONE;
807 goto do_followup_srst;
808 } else {
809 ata_port_printk(ap, KERN_INFO,

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876 ioread32(CQ + hcr_base),
877 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
878
879 iowrite32(0xFFFF, CC + hcr_base);
880 if (pmp != SATA_PMP_CTRL_PORT)
881 iowrite32(pmp, CQPMP + hcr_base);
882 iowrite32(1, CQ + hcr_base);
883
883 temp = ata_wait_register(CQ + hcr_base, 0x1, 0x1, 1, 5000);
884 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
884 if (temp & 0x1) {
885 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
886
887 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
888 ioread32(CQ + hcr_base),
889 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
890
891 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
892
893 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
894 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
895 DPRINTK("Serror = 0x%x\n", Serror);
896 goto err;
897 }
898
885 if (temp & 0x1) {
886 ata_port_printk(ap, KERN_WARNING, "ATA_SRST issue failed\n");
887
888 DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
889 ioread32(CQ + hcr_base),
890 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
891
892 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
893
894 DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
895 DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
896 DPRINTK("Serror = 0x%x\n", Serror);
897 goto err;
898 }
899
899 msleep(1);
900 ata_msleep(ap, 1);
900
901 /*
902 * SATA device enters reset state after receving a Control register
903 * FIS with SRST bit asserted and it awaits another H2D Control reg.
904 * FIS with SRST bit cleared, then the device does internal diags &
905 * initialization, followed by indicating it's initialization status
906 * using ATA signature D2H register FIS to the host controller.
907 */
908
909 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
910 0, 0, 5);
911
912 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
913 ata_tf_to_fis(&tf, pmp, 0, cfis);
914
915 if (pmp != SATA_PMP_CTRL_PORT)
916 iowrite32(pmp, CQPMP + hcr_base);
917 iowrite32(1, CQ + hcr_base);
901
902 /*
903 * SATA device enters reset state after receving a Control register
904 * FIS with SRST bit asserted and it awaits another H2D Control reg.
905 * FIS with SRST bit cleared, then the device does internal diags &
906 * initialization, followed by indicating it's initialization status
907 * using ATA signature D2H register FIS to the host controller.
908 */
909
910 sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
911 0, 0, 5);
912
913 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
914 ata_tf_to_fis(&tf, pmp, 0, cfis);
915
916 if (pmp != SATA_PMP_CTRL_PORT)
917 iowrite32(pmp, CQPMP + hcr_base);
918 iowrite32(1, CQ + hcr_base);
918 msleep(150); /* ?? */
919 ata_msleep(ap, 150); /* ?? */
919
920 /*
921 * The above command would have signalled an interrupt on command
922 * complete, which needs special handling, by clearing the Nth
923 * command bit of the CCreg
924 */
925 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
926

--- 530 unchanged lines hidden --- 		920
921 /*
922 * The above command would have signalled an interrupt on command
923 * complete, which needs special handling, by clearing the Nth
924 * command bit of the CCreg
925 */
926 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
927

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