libahci.c (6b7ae9545ad9875a289f4191c0216b473e313cb9) libahci.c (97750cebb3000a9cc08f8ce8dc8c7143be7d7201)
1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.

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562 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
563 return 0;
564
565 /* setting HBA to idle */
566 tmp &= ~PORT_CMD_START;
567 writel(tmp, port_mmio + PORT_CMD);
568
569 /* wait for engine to stop. This could be as long as 500 msec */
1/*
2 * libahci.c - Common AHCI SATA low-level routines
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.

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562 if ((tmp & (PORT_CMD_START | PORT_CMD_LIST_ON)) == 0)
563 return 0;
564
565 /* setting HBA to idle */
566 tmp &= ~PORT_CMD_START;
567 writel(tmp, port_mmio + PORT_CMD);
568
569 /* wait for engine to stop. This could be as long as 500 msec */
570 tmp = ata_wait_register(port_mmio + PORT_CMD,
570 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
571 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
572 if (tmp & PORT_CMD_LIST_ON)
573 return -EIO;
574
575 return 0;
576}
577EXPORT_SYMBOL_GPL(ahci_stop_engine);
578

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609 u32 tmp;
610
611 /* disable FIS reception */
612 tmp = readl(port_mmio + PORT_CMD);
613 tmp &= ~PORT_CMD_FIS_RX;
614 writel(tmp, port_mmio + PORT_CMD);
615
616 /* wait for completion, spec says 500ms, give it 1000 */
571 PORT_CMD_LIST_ON, PORT_CMD_LIST_ON, 1, 500);
572 if (tmp & PORT_CMD_LIST_ON)
573 return -EIO;
574
575 return 0;
576}
577EXPORT_SYMBOL_GPL(ahci_stop_engine);
578

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609 u32 tmp;
610
611 /* disable FIS reception */
612 tmp = readl(port_mmio + PORT_CMD);
613 tmp &= ~PORT_CMD_FIS_RX;
614 writel(tmp, port_mmio + PORT_CMD);
615
616 /* wait for completion, spec says 500ms, give it 1000 */
617 tmp = ata_wait_register(port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
617 tmp = ata_wait_register(ap, port_mmio + PORT_CMD, PORT_CMD_FIS_ON,
618 PORT_CMD_FIS_ON, 10, 1000);
619 if (tmp & PORT_CMD_FIS_ON)
620 return -EBUSY;
621
622 return 0;
623}
624
625static void ahci_power_up(struct ata_port *ap)

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666 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
667 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
668 cmd |= PORT_CMD_ICC_ACTIVE;
669
670 writel(cmd, port_mmio + PORT_CMD);
671 readl(port_mmio + PORT_CMD);
672
673 /* wait 10ms to be sure we've come out of LPM state */
618 PORT_CMD_FIS_ON, 10, 1000);
619 if (tmp & PORT_CMD_FIS_ON)
620 return -EBUSY;
621
622 return 0;
623}
624
625static void ahci_power_up(struct ata_port *ap)

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666 if (policy == ATA_LPM_MAX_POWER || !(hints & ATA_LPM_HIPM)) {
667 cmd &= ~(PORT_CMD_ASP | PORT_CMD_ALPE);
668 cmd |= PORT_CMD_ICC_ACTIVE;
669
670 writel(cmd, port_mmio + PORT_CMD);
671 readl(port_mmio + PORT_CMD);
672
673 /* wait 10ms to be sure we've come out of LPM state */
674 msleep(10);
674 ata_msleep(ap, 10);
675 } else {
676 cmd |= PORT_CMD_ALPE;
677 if (policy == ATA_LPM_MIN_POWER)
678 cmd |= PORT_CMD_ASP;
679
680 /* write out new cmd value */
681 writel(cmd, port_mmio + PORT_CMD);
682 }

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735 emp = &pp->em_priv[link->pmp];
736
737 /* EM Transmit bit maybe busy during init */
738 for (i = 0; i < EM_MAX_RETRY; i++) {
739 rc = ahci_transmit_led_message(ap,
740 emp->led_state,
741 4);
742 if (rc == -EBUSY)
675 } else {
676 cmd |= PORT_CMD_ALPE;
677 if (policy == ATA_LPM_MIN_POWER)
678 cmd |= PORT_CMD_ASP;
679
680 /* write out new cmd value */
681 writel(cmd, port_mmio + PORT_CMD);
682 }

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735 emp = &pp->em_priv[link->pmp];
736
737 /* EM Transmit bit maybe busy during init */
738 for (i = 0; i < EM_MAX_RETRY; i++) {
739 rc = ahci_transmit_led_message(ap,
740 emp->led_state,
741 4);
742 if (rc == -EBUSY)
743 msleep(1);
743 ata_msleep(ap, 1);
744 else
745 break;
746 }
747 }
748 }
749
750 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
751 ata_for_each_link(link, ap, EDGE)

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794 }
795
796 /*
797 * to perform host reset, OS should set HOST_RESET
798 * and poll until this bit is read to be "0".
799 * reset must complete within 1 second, or
800 * the hardware should be considered fried.
801 */
744 else
745 break;
746 }
747 }
748 }
749
750 if (ap->flags & ATA_FLAG_SW_ACTIVITY)
751 ata_for_each_link(link, ap, EDGE)

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794 }
795
796 /*
797 * to perform host reset, OS should set HOST_RESET
798 * and poll until this bit is read to be "0".
799 * reset must complete within 1 second, or
800 * the hardware should be considered fried.
801 */
802 tmp = ata_wait_register(mmio + HOST_CTL, HOST_RESET,
802 tmp = ata_wait_register(NULL, mmio + HOST_CTL, HOST_RESET,
803 HOST_RESET, 10, 1000);
804
805 if (tmp & HOST_RESET) {
806 dev_printk(KERN_ERR, host->dev,
807 "controller reset failed (0x%x)\n", tmp);
808 return -EIO;
809 }
810

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1174 }
1175
1176 /* perform CLO */
1177 tmp = readl(port_mmio + PORT_CMD);
1178 tmp |= PORT_CMD_CLO;
1179 writel(tmp, port_mmio + PORT_CMD);
1180
1181 rc = 0;
803 HOST_RESET, 10, 1000);
804
805 if (tmp & HOST_RESET) {
806 dev_printk(KERN_ERR, host->dev,
807 "controller reset failed (0x%x)\n", tmp);
808 return -EIO;
809 }
810

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1174 }
1175
1176 /* perform CLO */
1177 tmp = readl(port_mmio + PORT_CMD);
1178 tmp |= PORT_CMD_CLO;
1179 writel(tmp, port_mmio + PORT_CMD);
1180
1181 rc = 0;
1182 tmp = ata_wait_register(port_mmio + PORT_CMD,
1182 tmp = ata_wait_register(ap, port_mmio + PORT_CMD,
1183 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1184 if (tmp & PORT_CMD_CLO)
1185 rc = -EIO;
1186
1187 /* restart engine */
1188 out_restart:
1189 ahci_start_engine(ap);
1190 return rc;

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1204 /* prep the command */
1205 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1206 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1207
1208 /* issue & wait */
1209 writel(1, port_mmio + PORT_CMD_ISSUE);
1210
1211 if (timeout_msec) {
1183 PORT_CMD_CLO, PORT_CMD_CLO, 1, 500);
1184 if (tmp & PORT_CMD_CLO)
1185 rc = -EIO;
1186
1187 /* restart engine */
1188 out_restart:
1189 ahci_start_engine(ap);
1190 return rc;

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1204 /* prep the command */
1205 ata_tf_to_fis(tf, pmp, is_cmd, fis);
1206 ahci_fill_cmd_slot(pp, 0, cmd_fis_len | flags | (pmp << 12));
1207
1208 /* issue & wait */
1209 writel(1, port_mmio + PORT_CMD_ISSUE);
1210
1211 if (timeout_msec) {
1212 tmp = ata_wait_register(port_mmio + PORT_CMD_ISSUE, 0x1, 0x1,
1213 1, timeout_msec);
1212 tmp = ata_wait_register(ap, port_mmio + PORT_CMD_ISSUE,
1213 0x1, 0x1, 1, timeout_msec);
1214 if (tmp & 0x1) {
1215 ahci_kick_engine(ap);
1216 return -EBUSY;
1217 }
1218 } else
1219 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1220
1221 return 0;

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1252 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1253 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1254 rc = -EIO;
1255 reason = "1st FIS failed";
1256 goto fail;
1257 }
1258
1259 /* spec says at least 5us, but be generous and sleep for 1ms */
1214 if (tmp & 0x1) {
1215 ahci_kick_engine(ap);
1216 return -EBUSY;
1217 }
1218 } else
1219 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
1220
1221 return 0;

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1252 if (ahci_exec_polled_cmd(ap, pmp, &tf, 0,
1253 AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY, msecs)) {
1254 rc = -EIO;
1255 reason = "1st FIS failed";
1256 goto fail;
1257 }
1258
1259 /* spec says at least 5us, but be generous and sleep for 1ms */
1260 msleep(1);
1260 ata_msleep(ap, 1);
1261
1262 /* issue the second D2H Register FIS */
1263 tf.ctl &= ~ATA_SRST;
1264 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1265
1266 /* wait for link to become ready */
1267 rc = ata_wait_after_reset(link, deadline, check_ready);
1268 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {

--- 860 unchanged lines hidden --- 		1261
1262 /* issue the second D2H Register FIS */
1263 tf.ctl &= ~ATA_SRST;
1264 ahci_exec_polled_cmd(ap, pmp, &tf, 0, 0, 0);
1265
1266 /* wait for link to become ready */
1267 rc = ata_wait_after_reset(link, deadline, check_ready);
1268 if (rc == -EBUSY && hpriv->flags & AHCI_HFLAG_SRST_TOUT_IS_OFFLINE) {

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