gaudi2.c (dc934c183d43d30e49eacddc76b9882a7e3c1cde) gaudi2.c (e1ef053e08c9b56c0de0635beea75466e97a7383)
1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * Copyright 2020-2022 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8#include "gaudi2P.h"

--- 2426 unchanged lines hidden (view full) ---

2435 prop->first_available_user_sob[0] = GAUDI2_RESERVED_SOB_NUMBER +
2436 (num_sync_stream_queues * HL_RSVD_SOBS);
2437
2438 prop->first_available_user_mon[0] = GAUDI2_RESERVED_MON_NUMBER +
2439 (num_sync_stream_queues * HL_RSVD_MONS);
2440
2441 prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST;
2442 prop->tpc_interrupt_id = GAUDI2_IRQ_NUM_TPC_ASSERT;
1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * Copyright 2020-2022 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8#include "gaudi2P.h"

--- 2426 unchanged lines hidden (view full) ---

2435 prop->first_available_user_sob[0] = GAUDI2_RESERVED_SOB_NUMBER +
2436 (num_sync_stream_queues * HL_RSVD_SOBS);
2437
2438 prop->first_available_user_mon[0] = GAUDI2_RESERVED_MON_NUMBER +
2439 (num_sync_stream_queues * HL_RSVD_MONS);
2440
2441 prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST;
2442 prop->tpc_interrupt_id = GAUDI2_IRQ_NUM_TPC_ASSERT;
2443 prop->unexpected_user_error_interrupt_id = GAUDI2_IRQ_NUM_UNEXPECTED_ERROR;
2443
2444 prop->first_available_cq[0] = GAUDI2_RESERVED_CQ_NUMBER;
2445
2446 prop->fw_cpu_boot_dev_sts0_valid = false;
2447 prop->fw_cpu_boot_dev_sts1_valid = false;
2448 prop->hard_reset_done_by_fw = false;
2449 prop->gic_interrupts_enable = true;
2450

--- 890 unchanged lines hidden (view full) ---

3341static void gaudi2_user_interrupt_setup(struct hl_device *hdev)
3342{
3343 struct asic_fixed_properties *prop = &hdev->asic_prop;
3344 int i, j, k;
3345
3346 /* Initialize TPC interrupt */
3347 HL_USR_INTR_STRUCT_INIT(hdev->tpc_interrupt, hdev, 0, HL_USR_INTERRUPT_TPC);
3348
2444
2445 prop->first_available_cq[0] = GAUDI2_RESERVED_CQ_NUMBER;
2446
2447 prop->fw_cpu_boot_dev_sts0_valid = false;
2448 prop->fw_cpu_boot_dev_sts1_valid = false;
2449 prop->hard_reset_done_by_fw = false;
2450 prop->gic_interrupts_enable = true;
2451

--- 890 unchanged lines hidden (view full) ---

3342static void gaudi2_user_interrupt_setup(struct hl_device *hdev)
3343{
3344 struct asic_fixed_properties *prop = &hdev->asic_prop;
3345 int i, j, k;
3346
3347 /* Initialize TPC interrupt */
3348 HL_USR_INTR_STRUCT_INIT(hdev->tpc_interrupt, hdev, 0, HL_USR_INTERRUPT_TPC);
3349
3350 /* Initialize general purpose interrupt */
3351 HL_USR_INTR_STRUCT_INIT(hdev->unexpected_error_interrupt, hdev, 0,
3352 HL_USR_INTERRUPT_UNEXPECTED);
3353
3349 /* Initialize common user CQ interrupt */
3350 HL_USR_INTR_STRUCT_INIT(hdev->common_user_cq_interrupt, hdev,
3351 HL_COMMON_USER_CQ_INTERRUPT_ID, HL_USR_INTERRUPT_CQ);
3352
3353 /* Initialize common decoder interrupt */
3354 HL_USR_INTR_STRUCT_INIT(hdev->common_decoder_interrupt, hdev,
3355 HL_COMMON_DEC_INTERRUPT_ID, HL_USR_INTERRUPT_DECODER);
3356

--- 643 unchanged lines hidden (view full) ---

4000 case GAUDI2_IRQ_NUM_EVENT_QUEUE:
4001 return "gaudi2 cpu eq";
4002 case GAUDI2_IRQ_NUM_COMPLETION:
4003 return "gaudi2 completion";
4004 case GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ... GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM:
4005 return gaudi2_vdec_irq_name[irq_number - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM];
4006 case GAUDI2_IRQ_NUM_TPC_ASSERT:
4007 return "gaudi2 tpc assert";
3354 /* Initialize common user CQ interrupt */
3355 HL_USR_INTR_STRUCT_INIT(hdev->common_user_cq_interrupt, hdev,
3356 HL_COMMON_USER_CQ_INTERRUPT_ID, HL_USR_INTERRUPT_CQ);
3357
3358 /* Initialize common decoder interrupt */
3359 HL_USR_INTR_STRUCT_INIT(hdev->common_decoder_interrupt, hdev,
3360 HL_COMMON_DEC_INTERRUPT_ID, HL_USR_INTERRUPT_DECODER);
3361

--- 643 unchanged lines hidden (view full) ---

4005 case GAUDI2_IRQ_NUM_EVENT_QUEUE:
4006 return "gaudi2 cpu eq";
4007 case GAUDI2_IRQ_NUM_COMPLETION:
4008 return "gaudi2 completion";
4009 case GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ... GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM:
4010 return gaudi2_vdec_irq_name[irq_number - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM];
4011 case GAUDI2_IRQ_NUM_TPC_ASSERT:
4012 return "gaudi2 tpc assert";
4013 case GAUDI2_IRQ_NUM_UNEXPECTED_ERROR:
4014 return "gaudi2 tpc assert";
4008 case GAUDI2_IRQ_NUM_USER_FIRST ... GAUDI2_IRQ_NUM_USER_LAST:
4009 return "gaudi2 user completion";
4010 default:
4011 return "invalid";
4012 }
4013}
4014
4015static void gaudi2_dec_disable_msix(struct hl_device *hdev, u32 max_irq_num)

--- 104 unchanged lines hidden (view full) ---

4120 rc = request_threaded_irq(irq, hl_irq_handler_user_interrupt,
4121 hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT,
4122 gaudi2_irq_name(GAUDI2_IRQ_NUM_TPC_ASSERT), &hdev->tpc_interrupt);
4123 if (rc) {
4124 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
4125 goto free_dec_irq;
4126 }
4127
4015 case GAUDI2_IRQ_NUM_USER_FIRST ... GAUDI2_IRQ_NUM_USER_LAST:
4016 return "gaudi2 user completion";
4017 default:
4018 return "invalid";
4019 }
4020}
4021
4022static void gaudi2_dec_disable_msix(struct hl_device *hdev, u32 max_irq_num)

--- 104 unchanged lines hidden (view full) ---

4127 rc = request_threaded_irq(irq, hl_irq_handler_user_interrupt,
4128 hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT,
4129 gaudi2_irq_name(GAUDI2_IRQ_NUM_TPC_ASSERT), &hdev->tpc_interrupt);
4130 if (rc) {
4131 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
4132 goto free_dec_irq;
4133 }
4134
4135 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR);
4136 rc = request_irq(irq, hl_irq_handler_user_interrupt, 0,
4137 gaudi2_irq_name(GAUDI2_IRQ_NUM_UNEXPECTED_ERROR),
4138 &hdev->unexpected_error_interrupt);
4139 if (rc) {
4140 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
4141 goto free_tpc_irq;
4142 }
4143
4128 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, user_irq_init_cnt = 0;
4129 user_irq_init_cnt < prop->user_interrupt_count;
4130 i++, j++, user_irq_init_cnt++) {
4131
4132 irq = pci_irq_vector(hdev->pdev, i);
4133 rc = request_threaded_irq(irq, hl_irq_handler_user_interrupt,
4134 hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT,
4135 gaudi2_irq_name(i), &hdev->user_interrupt[j]);

--- 10 unchanged lines hidden (view full) ---

4146
4147free_user_irq:
4148 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count;
4149 i < GAUDI2_IRQ_NUM_USER_FIRST + user_irq_init_cnt ; i++, j++) {
4150
4151 irq = pci_irq_vector(hdev->pdev, i);
4152 free_irq(irq, &hdev->user_interrupt[j]);
4153 }
4144 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, user_irq_init_cnt = 0;
4145 user_irq_init_cnt < prop->user_interrupt_count;
4146 i++, j++, user_irq_init_cnt++) {
4147
4148 irq = pci_irq_vector(hdev->pdev, i);
4149 rc = request_threaded_irq(irq, hl_irq_handler_user_interrupt,
4150 hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT,
4151 gaudi2_irq_name(i), &hdev->user_interrupt[j]);

--- 10 unchanged lines hidden (view full) ---

4162
4163free_user_irq:
4164 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count;
4165 i < GAUDI2_IRQ_NUM_USER_FIRST + user_irq_init_cnt ; i++, j++) {
4166
4167 irq = pci_irq_vector(hdev->pdev, i);
4168 free_irq(irq, &hdev->user_interrupt[j]);
4169 }
4170 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR);
4171 free_irq(irq, &hdev->unexpected_error_interrupt);
4172free_tpc_irq:
4173 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
4174 free_irq(irq, &hdev->tpc_interrupt);
4154free_dec_irq:
4155 gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_DEC_LAST + 1);
4156free_event_irq:
4157 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
4158 free_irq(irq, cq);
4159
4160free_completion_irq:
4161 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);

--- 18 unchanged lines hidden (view full) ---

4180 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION));
4181
4182 for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ; i <= GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM ; i++) {
4183 irq = pci_irq_vector(hdev->pdev, i);
4184 synchronize_irq(irq);
4185 }
4186
4187 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT));
4175free_dec_irq:
4176 gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_DEC_LAST + 1);
4177free_event_irq:
4178 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
4179 free_irq(irq, cq);
4180
4181free_completion_irq:
4182 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);

--- 18 unchanged lines hidden (view full) ---

4201 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION));
4202
4203 for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ; i <= GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM ; i++) {
4204 irq = pci_irq_vector(hdev->pdev, i);
4205 synchronize_irq(irq);
4206 }
4207
4208 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT));
4209 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR));
4188
4189 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = 0 ; j < hdev->asic_prop.user_interrupt_count;
4190 i++, j++) {
4191 irq = pci_irq_vector(hdev->pdev, i);
4192 synchronize_irq(irq);
4193 }
4194
4195 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE));

--- 14 unchanged lines hidden (view full) ---

4210 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
4211 free_irq(irq, &hdev->event_queue);
4212
4213 gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1);
4214
4215 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
4216 free_irq(irq, &hdev->tpc_interrupt);
4217
4210
4211 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = 0 ; j < hdev->asic_prop.user_interrupt_count;
4212 i++, j++) {
4213 irq = pci_irq_vector(hdev->pdev, i);
4214 synchronize_irq(irq);
4215 }
4216
4217 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE));

--- 14 unchanged lines hidden (view full) ---

4232 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
4233 free_irq(irq, &hdev->event_queue);
4234
4235 gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1);
4236
4237 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
4238 free_irq(irq, &hdev->tpc_interrupt);
4239
4240 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_UNEXPECTED_ERROR);
4241 free_irq(irq, &hdev->unexpected_error_interrupt);
4242
4218 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, k = 0;
4219 k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) {
4220
4221 irq = pci_irq_vector(hdev->pdev, i);
4222 free_irq(irq, &hdev->user_interrupt[j]);
4223 }
4224
4225 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);

--- 6939 unchanged lines hidden --- 		4243 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, k = 0;
4244 k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) {
4245
4246 irq = pci_irq_vector(hdev->pdev, i);
4247 free_irq(irq, &hdev->user_interrupt[j]);
4248 }
4249
4250 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);

--- 6939 unchanged lines hidden ---