gaudi2.c (601223589990101edc0bf6adccaf8cd376a431cc) gaudi2.c (4713ace3246644519bf93cc8ea6e44efe57fc3ec)
1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * Copyright 2020-2022 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8#include "gaudi2P.h"

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2343
2344 prop->first_available_user_sob[0] = GAUDI2_RESERVED_SOB_NUMBER +
2345 (num_sync_stream_queues * HL_RSVD_SOBS);
2346
2347 prop->first_available_user_mon[0] = GAUDI2_RESERVED_MON_NUMBER +
2348 (num_sync_stream_queues * HL_RSVD_MONS);
2349
2350 prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST;
1// SPDX-License-Identifier: GPL-2.0
2
3/*
4 * Copyright 2020-2022 HabanaLabs, Ltd.
5 * All Rights Reserved.
6 */
7
8#include "gaudi2P.h"

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2343
2344 prop->first_available_user_sob[0] = GAUDI2_RESERVED_SOB_NUMBER +
2345 (num_sync_stream_queues * HL_RSVD_SOBS);
2346
2347 prop->first_available_user_mon[0] = GAUDI2_RESERVED_MON_NUMBER +
2348 (num_sync_stream_queues * HL_RSVD_MONS);
2349
2350 prop->first_available_user_interrupt = GAUDI2_IRQ_NUM_USER_FIRST;
2351 prop->tpc_interrupt_id = GAUDI2_IRQ_NUM_TPC_ASSERT;
2351
2352 prop->first_available_cq[0] = GAUDI2_RESERVED_CQ_NUMBER;
2353
2354 prop->fw_cpu_boot_dev_sts0_valid = false;
2355 prop->fw_cpu_boot_dev_sts1_valid = false;
2356 prop->hard_reset_done_by_fw = false;
2357 prop->gic_interrupts_enable = true;
2358

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3230 region->used = 1;
3231}
3232
3233static void gaudi2_user_interrupt_setup(struct hl_device *hdev)
3234{
3235 struct asic_fixed_properties *prop = &hdev->asic_prop;
3236 int i, j, k;
3237
2352
2353 prop->first_available_cq[0] = GAUDI2_RESERVED_CQ_NUMBER;
2354
2355 prop->fw_cpu_boot_dev_sts0_valid = false;
2356 prop->fw_cpu_boot_dev_sts1_valid = false;
2357 prop->hard_reset_done_by_fw = false;
2358 prop->gic_interrupts_enable = true;
2359

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3231 region->used = 1;
3232}
3233
3234static void gaudi2_user_interrupt_setup(struct hl_device *hdev)
3235{
3236 struct asic_fixed_properties *prop = &hdev->asic_prop;
3237 int i, j, k;
3238
3239 /* Initialize TPC interrupt */
3240 HL_USR_INTR_STRUCT_INIT(hdev->tpc_interrupt, hdev, 0, HL_USR_INTERRUPT_TPC);
3241
3238 /* Initialize common user CQ interrupt */
3239 HL_USR_INTR_STRUCT_INIT(hdev->common_user_cq_interrupt, hdev,
3240 HL_COMMON_USER_CQ_INTERRUPT_ID, HL_USR_INTERRUPT_CQ);
3241
3242 /* Initialize common decoder interrupt */
3243 HL_USR_INTR_STRUCT_INIT(hdev->common_decoder_interrupt, hdev,
3244 HL_COMMON_DEC_INTERRUPT_ID, HL_USR_INTERRUPT_DECODER);
3245

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3887{
3888 switch (irq_number) {
3889 case GAUDI2_IRQ_NUM_EVENT_QUEUE:
3890 return "gaudi2 cpu eq";
3891 case GAUDI2_IRQ_NUM_COMPLETION:
3892 return "gaudi2 completion";
3893 case GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ... GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM:
3894 return gaudi2_vdec_irq_name[irq_number - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM];
3242 /* Initialize common user CQ interrupt */
3243 HL_USR_INTR_STRUCT_INIT(hdev->common_user_cq_interrupt, hdev,
3244 HL_COMMON_USER_CQ_INTERRUPT_ID, HL_USR_INTERRUPT_CQ);
3245
3246 /* Initialize common decoder interrupt */
3247 HL_USR_INTR_STRUCT_INIT(hdev->common_decoder_interrupt, hdev,
3248 HL_COMMON_DEC_INTERRUPT_ID, HL_USR_INTERRUPT_DECODER);
3249

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3891{
3892 switch (irq_number) {
3893 case GAUDI2_IRQ_NUM_EVENT_QUEUE:
3894 return "gaudi2 cpu eq";
3895 case GAUDI2_IRQ_NUM_COMPLETION:
3896 return "gaudi2 completion";
3897 case GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ... GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM:
3898 return gaudi2_vdec_irq_name[irq_number - GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM];
3899 case GAUDI2_IRQ_NUM_TPC_ASSERT:
3900 return "gaudi2 tpc assert";
3895 case GAUDI2_IRQ_NUM_USER_FIRST ... GAUDI2_IRQ_NUM_USER_LAST:
3896 return "gaudi2 user completion";
3897 default:
3898 return "invalid";
3899 }
3900}
3901
3902static void gaudi2_dec_disable_msix(struct hl_device *hdev, u32 max_irq_num)

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3999 }
4000
4001 rc = gaudi2_dec_enable_msix(hdev);
4002 if (rc) {
4003 dev_err(hdev->dev, "Failed to enable decoder IRQ");
4004 goto free_event_irq;
4005 }
4006
3901 case GAUDI2_IRQ_NUM_USER_FIRST ... GAUDI2_IRQ_NUM_USER_LAST:
3902 return "gaudi2 user completion";
3903 default:
3904 return "invalid";
3905 }
3906}
3907
3908static void gaudi2_dec_disable_msix(struct hl_device *hdev, u32 max_irq_num)

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4005 }
4006
4007 rc = gaudi2_dec_enable_msix(hdev);
4008 if (rc) {
4009 dev_err(hdev->dev, "Failed to enable decoder IRQ");
4010 goto free_event_irq;
4011 }
4012
4013 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
4014 rc = request_threaded_irq(irq, hl_irq_handler_user_interrupt,
4015 hl_irq_user_interrupt_thread_handler, IRQF_ONESHOT,
4016 gaudi2_irq_name(GAUDI2_IRQ_NUM_TPC_ASSERT), &hdev->tpc_interrupt);
4017 if (rc) {
4018 dev_err(hdev->dev, "Failed to request IRQ %d", irq);
4019 goto free_dec_irq;
4020 }
4021
4007 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, user_irq_init_cnt = 0;
4008 user_irq_init_cnt < prop->user_interrupt_count;
4009 i++, j++, user_irq_init_cnt++) {
4010
4011 irq = pci_irq_vector(hdev->pdev, i);
4012 irq_handler = hl_irq_handler_user_interrupt;
4013
4014 rc = request_threaded_irq(irq, irq_handler, hl_irq_user_interrupt_thread_handler,

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4026
4027free_user_irq:
4028 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count;
4029 i < GAUDI2_IRQ_NUM_USER_FIRST + user_irq_init_cnt ; i++, j++) {
4030
4031 irq = pci_irq_vector(hdev->pdev, i);
4032 free_irq(irq, &hdev->user_interrupt[j]);
4033 }
4022 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, user_irq_init_cnt = 0;
4023 user_irq_init_cnt < prop->user_interrupt_count;
4024 i++, j++, user_irq_init_cnt++) {
4025
4026 irq = pci_irq_vector(hdev->pdev, i);
4027 irq_handler = hl_irq_handler_user_interrupt;
4028
4029 rc = request_threaded_irq(irq, irq_handler, hl_irq_user_interrupt_thread_handler,

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4041
4042free_user_irq:
4043 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count;
4044 i < GAUDI2_IRQ_NUM_USER_FIRST + user_irq_init_cnt ; i++, j++) {
4045
4046 irq = pci_irq_vector(hdev->pdev, i);
4047 free_irq(irq, &hdev->user_interrupt[j]);
4048 }
4034
4035 gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1);
4036
4049free_dec_irq:
4050 gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_DEC_LAST + 1);
4037free_event_irq:
4038 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
4039 free_irq(irq, cq);
4040
4041free_completion_irq:
4042 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);
4043 free_irq(irq, cq);
4044

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4060 /* Wait for all pending IRQs to be finished */
4061 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION));
4062
4063 for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ; i <= GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM ; i++) {
4064 irq = pci_irq_vector(hdev->pdev, i);
4065 synchronize_irq(irq);
4066 }
4067
4051free_event_irq:
4052 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
4053 free_irq(irq, cq);
4054
4055free_completion_irq:
4056 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);
4057 free_irq(irq, cq);
4058

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4074 /* Wait for all pending IRQs to be finished */
4075 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION));
4076
4077 for (i = GAUDI2_IRQ_NUM_DCORE0_DEC0_NRM ; i <= GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM ; i++) {
4078 irq = pci_irq_vector(hdev->pdev, i);
4079 synchronize_irq(irq);
4080 }
4081
4082 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT));
4083
4068 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = 0 ; j < hdev->asic_prop.user_interrupt_count;
4069 i++, j++) {
4070 irq = pci_irq_vector(hdev->pdev, i);
4071 synchronize_irq(irq);
4072 }
4073
4074 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE));
4075}

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4086
4087 gaudi2_sync_irqs(hdev);
4088
4089 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
4090 free_irq(irq, &hdev->event_queue);
4091
4092 gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1);
4093
4084 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = 0 ; j < hdev->asic_prop.user_interrupt_count;
4085 i++, j++) {
4086 irq = pci_irq_vector(hdev->pdev, i);
4087 synchronize_irq(irq);
4088 }
4089
4090 synchronize_irq(pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE));
4091}

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4102
4103 gaudi2_sync_irqs(hdev);
4104
4105 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_EVENT_QUEUE);
4106 free_irq(irq, &hdev->event_queue);
4107
4108 gaudi2_dec_disable_msix(hdev, GAUDI2_IRQ_NUM_SHARED_DEC1_ABNRM + 1);
4109
4110 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_TPC_ASSERT);
4111 free_irq(irq, &hdev->tpc_interrupt);
4112
4094 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, k = 0;
4095 k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) {
4096
4097 irq = pci_irq_vector(hdev->pdev, i);
4098 free_irq(irq, &hdev->user_interrupt[j]);
4099 }
4100
4101 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);

--- 6672 unchanged lines hidden --- 		4113 for (i = GAUDI2_IRQ_NUM_USER_FIRST, j = prop->user_dec_intr_count, k = 0;
4114 k < hdev->asic_prop.user_interrupt_count ; i++, j++, k++) {
4115
4116 irq = pci_irq_vector(hdev->pdev, i);
4117 free_irq(irq, &hdev->user_interrupt[j]);
4118 }
4119
4120 irq = pci_irq_vector(hdev->pdev, GAUDI2_IRQ_NUM_COMPLETION);

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