mmconfig-shared.c (ecd740c6f2f092b90b95fa35f757973589eaaca2) mmconfig-shared.c (64474b5235e83cc5e6002dcdb37145850ad86194)
1/*
2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
4 *
5 * This code does:
6 * - known chipset handling
7 * - ACPI decoding and validation
8 *

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26
27/* Indicate if the mmcfg resources have been placed into the resource table. */
28static bool pci_mmcfg_running_state;
29static bool pci_mmcfg_arch_init_failed;
30static DEFINE_MUTEX(pci_mmcfg_lock);
31
32LIST_HEAD(pci_mmcfg_list);
33
1/*
2 * mmconfig-shared.c - Low-level direct PCI config space access via
3 * MMCONFIG - common code between i386 and x86-64.
4 *
5 * This code does:
6 * - known chipset handling
7 * - ACPI decoding and validation
8 *

--- 17 unchanged lines hidden (view full) ---

26
27/* Indicate if the mmcfg resources have been placed into the resource table. */
28static bool pci_mmcfg_running_state;
29static bool pci_mmcfg_arch_init_failed;
30static DEFINE_MUTEX(pci_mmcfg_lock);
31
32LIST_HEAD(pci_mmcfg_list);
33
34static __init void pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
34static void __init pci_mmconfig_remove(struct pci_mmcfg_region *cfg)
35{
36 if (cfg->res.parent)
37 release_resource(&cfg->res);
38 list_del(&cfg->list);
39 kfree(cfg);
40}
41
35{
36 if (cfg->res.parent)
37 release_resource(&cfg->res);
38 list_del(&cfg->list);
39 kfree(cfg);
40}
41
42static __init void free_all_mmcfg(void)
42static void __init free_all_mmcfg(void)
43{
44 struct pci_mmcfg_region *cfg, *tmp;
45
46 pci_mmcfg_arch_free();
47 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
48 pci_mmconfig_remove(cfg);
49}
50

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88 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
89 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
90 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
91 res->name = new->name;
92
93 return new;
94}
95
43{
44 struct pci_mmcfg_region *cfg, *tmp;
45
46 pci_mmcfg_arch_free();
47 list_for_each_entry_safe(cfg, tmp, &pci_mmcfg_list, list)
48 pci_mmconfig_remove(cfg);
49}
50

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88 res->flags = IORESOURCE_MEM | IORESOURCE_BUSY;
89 snprintf(new->name, PCI_MMCFG_RESOURCE_NAME_LEN,
90 "PCI MMCONFIG %04x [bus %02x-%02x]", segment, start, end);
91 res->name = new->name;
92
93 return new;
94}
95
96static __init struct pci_mmcfg_region *pci_mmconfig_add(int segment, int start,
96static struct pci_mmcfg_region *__init pci_mmconfig_add(int segment, int start,
97 int end, u64 addr)
98{
99 struct pci_mmcfg_region *new;
100
101 new = pci_mmconfig_alloc(segment, start, end, addr);
102 if (new) {
103 mutex_lock(&pci_mmcfg_lock);
104 list_add_sorted(new);

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120 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
121 if (cfg->segment == segment &&
122 cfg->start_bus <= bus && bus <= cfg->end_bus)
123 return cfg;
124
125 return NULL;
126}
127
97 int end, u64 addr)
98{
99 struct pci_mmcfg_region *new;
100
101 new = pci_mmconfig_alloc(segment, start, end, addr);
102 if (new) {
103 mutex_lock(&pci_mmcfg_lock);
104 list_add_sorted(new);

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120 list_for_each_entry_rcu(cfg, &pci_mmcfg_list, list)
121 if (cfg->segment == segment &&
122 cfg->start_bus <= bus && bus <= cfg->end_bus)
123 return cfg;
124
125 return NULL;
126}
127
128static const char __init *pci_mmcfg_e7520(void)
128static const char *__init pci_mmcfg_e7520(void)
129{
130 u32 win;
131 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
132
133 win = win & 0xf000;
134 if (win == 0x0000 || win == 0xf000)
135 return NULL;
136
137 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
138 return NULL;
139
140 return "Intel Corporation E7520 Memory Controller Hub";
141}
142
129{
130 u32 win;
131 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0xce, 2, &win);
132
133 win = win & 0xf000;
134 if (win == 0x0000 || win == 0xf000)
135 return NULL;
136
137 if (pci_mmconfig_add(0, 0, 255, win << 16) == NULL)
138 return NULL;
139
140 return "Intel Corporation E7520 Memory Controller Hub";
141}
142
143static const char __init *pci_mmcfg_intel_945(void)
143static const char *__init pci_mmcfg_intel_945(void)
144{
145 u32 pciexbar, mask = 0, len = 0;
146
147 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
148
149 /* Enable bit */
150 if (!(pciexbar & 1))
151 return NULL;

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179 return NULL;
180
181 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
182 return NULL;
183
184 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
185}
186
144{
145 u32 pciexbar, mask = 0, len = 0;
146
147 raw_pci_ops->read(0, 0, PCI_DEVFN(0, 0), 0x48, 4, &pciexbar);
148
149 /* Enable bit */
150 if (!(pciexbar & 1))
151 return NULL;

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179 return NULL;
180
181 if (pci_mmconfig_add(0, 0, (len >> 20) - 1, pciexbar & mask) == NULL)
182 return NULL;
183
184 return "Intel Corporation 945G/GZ/P/PL Express Memory Controller Hub";
185}
186
187static const char __init *pci_mmcfg_amd_fam10h(void)
187static const char *__init pci_mmcfg_amd_fam10h(void)
188{
189 u32 low, high, address;
190 u64 base, msr;
191 int i;
192 unsigned segnbits = 0, busnbits, end_bus;
193
194 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
195 return NULL;

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230 free_all_mmcfg();
231 return NULL;
232 }
233
234 return "AMD Family 10h NB";
235}
236
237static bool __initdata mcp55_checked;
188{
189 u32 low, high, address;
190 u64 base, msr;
191 int i;
192 unsigned segnbits = 0, busnbits, end_bus;
193
194 if (!(pci_probe & PCI_CHECK_ENABLE_AMD_MMCONF))
195 return NULL;

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230 free_all_mmcfg();
231 return NULL;
232 }
233
234 return "AMD Family 10h NB";
235}
236
237static bool __initdata mcp55_checked;
238static const char __init *pci_mmcfg_nvidia_mcp55(void)
238static const char *__init pci_mmcfg_nvidia_mcp55(void)
239{
240 int bus;
241 int mcp55_mmconf_found = 0;
242
243 static const u32 extcfg_regnum = 0x90;
244 static const u32 extcfg_regsize = 4;
245 static const u32 extcfg_enable_mask = 1<<31;
246 static const u32 extcfg_start_mask = 0xff<<16;

--- 540 unchanged lines hidden --- 		239{
240 int bus;
241 int mcp55_mmconf_found = 0;
242
243 static const u32 extcfg_regnum = 0x90;
244 static const u32 extcfg_regsize = 4;
245 static const u32 extcfg_enable_mask = 1<<31;
246 static const u32 extcfg_start_mask = 0xff<<16;

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