x86.c (cb84b55f6cde26c7c17beaf87da08645ae6ccbf9) x86.c (fc78f51938e1ea866daa2045851b2e5681371668)
1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008

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477void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
478{
479 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
480}
481EXPORT_SYMBOL_GPL(kvm_lmsw);
482
483void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
484{
1/*
2 * Kernel-based Virtual Machine driver for Linux
3 *
4 * derived from drivers/kvm/kvm_main.c
5 *
6 * Copyright (C) 2006 Qumranet, Inc.
7 * Copyright (C) 2008 Qumranet, Inc.
8 * Copyright IBM Corporation, 2008

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477void kvm_lmsw(struct kvm_vcpu *vcpu, unsigned long msw)
478{
479 kvm_set_cr0(vcpu, (vcpu->arch.cr0 & ~0x0ful) | (msw & 0x0f));
480}
481EXPORT_SYMBOL_GPL(kvm_lmsw);
482
483void kvm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
484{
485 unsigned long old_cr4 = vcpu->arch.cr4;
485 unsigned long old_cr4 = kvm_read_cr4(vcpu);
486 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
487
488 if (cr4 & CR4_RESERVED_BITS) {
489 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
490 kvm_inject_gp(vcpu, 0);
491 return;
492 }
493

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1894 /*
1895 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1896 * reporting is disabled for the bank
1897 */
1898 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1899 return 0;
1900 if (mce->status & MCI_STATUS_UC) {
1901 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
486 unsigned long pdptr_bits = X86_CR4_PGE | X86_CR4_PSE | X86_CR4_PAE;
487
488 if (cr4 & CR4_RESERVED_BITS) {
489 printk(KERN_DEBUG "set_cr4: #GP, reserved bits\n");
490 kvm_inject_gp(vcpu, 0);
491 return;
492 }
493

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1894 /*
1895 * if IA32_MCi_CTL is not all 1s, the uncorrected error
1896 * reporting is disabled for the bank
1897 */
1898 if ((mce->status & MCI_STATUS_UC) && banks[0] != ~(u64)0)
1899 return 0;
1900 if (mce->status & MCI_STATUS_UC) {
1901 if ((vcpu->arch.mcg_status & MCG_STATUS_MCIP) ||
1902 !(vcpu->arch.cr4 & X86_CR4_MCE)) {
1902 !kvm_read_cr4_bits(vcpu, X86_CR4_MCE)) {
1903 printk(KERN_DEBUG "kvm: set_mce: "
1904 "injects mce exception while "
1905 "previous one is in progress!\n");
1906 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1907 return 0;
1908 }
1909 if (banks[1] & MCI_STATUS_VAL)
1910 mce->status |= MCI_STATUS_OVER;

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3611 kvm_lmsw(vcpu, msw);
3612 *rflags = kvm_get_rflags(vcpu);
3613}
3614
3615unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3616{
3617 unsigned long value;
3618
1903 printk(KERN_DEBUG "kvm: set_mce: "
1904 "injects mce exception while "
1905 "previous one is in progress!\n");
1906 set_bit(KVM_REQ_TRIPLE_FAULT, &vcpu->requests);
1907 return 0;
1908 }
1909 if (banks[1] & MCI_STATUS_VAL)
1910 mce->status |= MCI_STATUS_OVER;

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3611 kvm_lmsw(vcpu, msw);
3612 *rflags = kvm_get_rflags(vcpu);
3613}
3614
3615unsigned long realmode_get_cr(struct kvm_vcpu *vcpu, int cr)
3616{
3617 unsigned long value;
3618
3619 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
3620 switch (cr) {
3621 case 0:
3622 value = vcpu->arch.cr0;
3623 break;
3624 case 2:
3625 value = vcpu->arch.cr2;
3626 break;
3627 case 3:
3628 value = vcpu->arch.cr3;
3629 break;
3630 case 4:
3619 switch (cr) {
3620 case 0:
3621 value = vcpu->arch.cr0;
3622 break;
3623 case 2:
3624 value = vcpu->arch.cr2;
3625 break;
3626 case 3:
3627 value = vcpu->arch.cr3;
3628 break;
3629 case 4:
3631 value = vcpu->arch.cr4;
3630 value = kvm_read_cr4(vcpu);
3632 break;
3633 case 8:
3634 value = kvm_get_cr8(vcpu);
3635 break;
3636 default:
3637 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3638 return 0;
3639 }

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3651 break;
3652 case 2:
3653 vcpu->arch.cr2 = val;
3654 break;
3655 case 3:
3656 kvm_set_cr3(vcpu, val);
3657 break;
3658 case 4:
3631 break;
3632 case 8:
3633 value = kvm_get_cr8(vcpu);
3634 break;
3635 default:
3636 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3637 return 0;
3638 }

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3650 break;
3651 case 2:
3652 vcpu->arch.cr2 = val;
3653 break;
3654 case 3:
3655 kvm_set_cr3(vcpu, val);
3656 break;
3657 case 4:
3659 kvm_set_cr4(vcpu, mk_cr_64(vcpu->arch.cr4, val));
3658 kvm_set_cr4(vcpu, mk_cr_64(kvm_read_cr4(vcpu), val));
3660 break;
3661 case 8:
3662 kvm_set_cr8(vcpu, val & 0xfUL);
3663 break;
3664 default:
3665 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3666 }
3667}

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4232
4233 kvm_x86_ops->get_idt(vcpu, &dt);
4234 sregs->idt.limit = dt.limit;
4235 sregs->idt.base = dt.base;
4236 kvm_x86_ops->get_gdt(vcpu, &dt);
4237 sregs->gdt.limit = dt.limit;
4238 sregs->gdt.base = dt.base;
4239
3659 break;
3660 case 8:
3661 kvm_set_cr8(vcpu, val & 0xfUL);
3662 break;
3663 default:
3664 vcpu_printf(vcpu, "%s: unexpected cr %u\n", __func__, cr);
3665 }
3666}

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4231
4232 kvm_x86_ops->get_idt(vcpu, &dt);
4233 sregs->idt.limit = dt.limit;
4234 sregs->idt.base = dt.base;
4235 kvm_x86_ops->get_gdt(vcpu, &dt);
4236 sregs->gdt.limit = dt.limit;
4237 sregs->gdt.base = dt.base;
4238
4240 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4241 sregs->cr0 = vcpu->arch.cr0;
4242 sregs->cr2 = vcpu->arch.cr2;
4243 sregs->cr3 = vcpu->arch.cr3;
4239 sregs->cr0 = vcpu->arch.cr0;
4240 sregs->cr2 = vcpu->arch.cr2;
4241 sregs->cr3 = vcpu->arch.cr3;
4244 sregs->cr4 = vcpu->arch.cr4;
4242 sregs->cr4 = kvm_read_cr4(vcpu);
4245 sregs->cr8 = kvm_get_cr8(vcpu);
4246 sregs->efer = vcpu->arch.shadow_efer;
4247 sregs->apic_base = kvm_get_apic_base(vcpu);
4248
4249 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
4250
4251 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
4252 set_bit(vcpu->arch.interrupt.nr,

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4732 vcpu->arch.cr3 = sregs->cr3;
4733
4734 kvm_set_cr8(vcpu, sregs->cr8);
4735
4736 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
4737 kvm_x86_ops->set_efer(vcpu, sregs->efer);
4738 kvm_set_apic_base(vcpu, sregs->apic_base);
4739
4243 sregs->cr8 = kvm_get_cr8(vcpu);
4244 sregs->efer = vcpu->arch.shadow_efer;
4245 sregs->apic_base = kvm_get_apic_base(vcpu);
4246
4247 memset(sregs->interrupt_bitmap, 0, sizeof sregs->interrupt_bitmap);
4248
4249 if (vcpu->arch.interrupt.pending && !vcpu->arch.interrupt.soft)
4250 set_bit(vcpu->arch.interrupt.nr,

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4730 vcpu->arch.cr3 = sregs->cr3;
4731
4732 kvm_set_cr8(vcpu, sregs->cr8);
4733
4734 mmu_reset_needed |= vcpu->arch.shadow_efer != sregs->efer;
4735 kvm_x86_ops->set_efer(vcpu, sregs->efer);
4736 kvm_set_apic_base(vcpu, sregs->apic_base);
4737
4740 kvm_x86_ops->decache_cr4_guest_bits(vcpu);
4741
4742 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
4743 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
4744 vcpu->arch.cr0 = sregs->cr0;
4745
4738 mmu_reset_needed |= vcpu->arch.cr0 != sregs->cr0;
4739 kvm_x86_ops->set_cr0(vcpu, sregs->cr0);
4740 vcpu->arch.cr0 = sregs->cr0;
4741
4746 mmu_reset_needed |= vcpu->arch.cr4 != sregs->cr4;
4742 mmu_reset_needed |= kvm_read_cr4(vcpu) != sregs->cr4;
4747 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4748 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
4749 load_pdptrs(vcpu, vcpu->arch.cr3);
4750 mmu_reset_needed = 1;
4751 }
4752
4753 if (mmu_reset_needed)
4754 kvm_mmu_reset_context(vcpu);

--- 582 unchanged lines hidden --- 		4743 kvm_x86_ops->set_cr4(vcpu, sregs->cr4);
4744 if (!is_long_mode(vcpu) && is_pae(vcpu)) {
4745 load_pdptrs(vcpu, vcpu->arch.cr3);
4746 mmu_reset_needed = 1;
4747 }
4748
4749 if (mmu_reset_needed)
4750 kvm_mmu_reset_context(vcpu);

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