mtrr.c (9ae38b4fb13597ce1821376d23958bbe4976c759) mtrr.c (34a83deac31cd9fdecef331578422095af2db4b0)
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * vMTRR implementation
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
7 * Copyright(C) 2015 Intel Corporation.
8 *

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29{
30 /* MTRR base MSRs use even numbers, masks use odd numbers. */
31 return !(msr & 0x1);
32}
33
34static struct kvm_mtrr_range *var_mtrr_msr_to_range(struct kvm_vcpu *vcpu,
35 unsigned int msr)
36{
1// SPDX-License-Identifier: GPL-2.0-only
2/*
3 * vMTRR implementation
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
7 * Copyright(C) 2015 Intel Corporation.
8 *

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29{
30 /* MTRR base MSRs use even numbers, masks use odd numbers. */
31 return !(msr & 0x1);
32}
33
34static struct kvm_mtrr_range *var_mtrr_msr_to_range(struct kvm_vcpu *vcpu,
35 unsigned int msr)
36{
37 int index = (msr - 0x200) / 2;
37 int index = (msr - MTRRphysBase_MSR(0)) / 2;
38
39 return &vcpu->arch.mtrr_state.var_ranges[index];
40}
41
42static bool msr_mtrr_valid(unsigned msr)
43{
44 switch (msr) {
38
39 return &vcpu->arch.mtrr_state.var_ranges[index];
40}
41
42static bool msr_mtrr_valid(unsigned msr)
43{
44 switch (msr) {
45 case 0x200 ... 0x200 + 2 * KVM_NR_VAR_MTRR - 1:
45 case MTRRphysBase_MSR(0) ... MTRRphysMask_MSR(KVM_NR_VAR_MTRR - 1):
46 case MSR_MTRRfix64K_00000:
47 case MSR_MTRRfix16K_80000:
48 case MSR_MTRRfix16K_A0000:
49 case MSR_MTRRfix4K_C0000:
50 case MSR_MTRRfix4K_C8000:
51 case MSR_MTRRfix4K_D0000:
52 case MSR_MTRRfix4K_D8000:
53 case MSR_MTRRfix4K_E0000:

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83 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
84 for (i = 0; i < 8 ; i++)
85 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
86 return false;
87 return true;
88 }
89
90 /* variable MTRRs */
46 case MSR_MTRRfix64K_00000:
47 case MSR_MTRRfix16K_80000:
48 case MSR_MTRRfix16K_A0000:
49 case MSR_MTRRfix4K_C0000:
50 case MSR_MTRRfix4K_C8000:
51 case MSR_MTRRfix4K_D0000:
52 case MSR_MTRRfix4K_D8000:
53 case MSR_MTRRfix4K_E0000:

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83 } else if (msr >= MSR_MTRRfix64K_00000 && msr <= MSR_MTRRfix4K_F8000) {
84 for (i = 0; i < 8 ; i++)
85 if (!valid_mtrr_type((data >> (i * 8)) & 0xff))
86 return false;
87 return true;
88 }
89
90 /* variable MTRRs */
91 WARN_ON(!(msr >= 0x200 && msr < 0x200 + 2 * KVM_NR_VAR_MTRR));
91 WARN_ON(!(msr >= MTRRphysBase_MSR(0) &&
92 msr <= MTRRphysMask_MSR(KVM_NR_VAR_MTRR - 1)));
92
93 mask = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
94 if ((msr & 1) == 0) {
95 /* MTRR base */
96 if (!valid_mtrr_type(data & 0xff))
97 return false;
98 mask |= 0xf00;
99 } else

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94 mask = kvm_vcpu_reserved_gpa_bits_raw(vcpu);
95 if ((msr & 1) == 0) {
96 /* MTRR base */
97 if (!valid_mtrr_type(data & 0xff))
98 return false;
99 mask |= 0xf00;
100 } else

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