mmu.h (6548698f929814375fa5d62ae1db96959b0418c1) mmu.h (fc78f51938e1ea866daa2045851b2e5681371668)
1#ifndef __KVM_X86_MMU_H
2#define __KVM_X86_MMU_H
3
4#include <linux/kvm_host.h>
1#ifndef __KVM_X86_MMU_H
2#define __KVM_X86_MMU_H
3
4#include <linux/kvm_host.h>
5#include "kvm_cache_regs.h"
5
6#define PT64_PT_BITS 9
7#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
8#define PT32_PT_BITS 10
9#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
10
11#define PT_WRITABLE_SHIFT 1
12

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59 return vcpu->arch.shadow_efer & EFER_LMA;
60#else
61 return 0;
62#endif
63}
64
65static inline int is_pae(struct kvm_vcpu *vcpu)
66{
6
7#define PT64_PT_BITS 9
8#define PT64_ENT_PER_PAGE (1 << PT64_PT_BITS)
9#define PT32_PT_BITS 10
10#define PT32_ENT_PER_PAGE (1 << PT32_PT_BITS)
11
12#define PT_WRITABLE_SHIFT 1
13

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60 return vcpu->arch.shadow_efer & EFER_LMA;
61#else
62 return 0;
63#endif
64}
65
66static inline int is_pae(struct kvm_vcpu *vcpu)
67{
67 return vcpu->arch.cr4 & X86_CR4_PAE;
68 return kvm_read_cr4_bits(vcpu, X86_CR4_PAE);
68}
69
70static inline int is_pse(struct kvm_vcpu *vcpu)
71{
69}
70
71static inline int is_pse(struct kvm_vcpu *vcpu)
72{
72 return vcpu->arch.cr4 & X86_CR4_PSE;
73 return kvm_read_cr4_bits(vcpu, X86_CR4_PSE);
73}
74
75static inline int is_paging(struct kvm_vcpu *vcpu)
76{
77 return vcpu->arch.cr0 & X86_CR0_PG;
78}
79
80static inline int is_present_gpte(unsigned long pte)
81{
82 return pte & PT_PRESENT_MASK;
83}
84
85#endif
74}
75
76static inline int is_paging(struct kvm_vcpu *vcpu)
77{
78 return vcpu->arch.cr0 & X86_CR0_PG;
79}
80
81static inline int is_present_gpte(unsigned long pte)
82{
83 return pte & PT_PRESENT_MASK;
84}
85
86#endif