lapic.c (83d4c286931c9d28c5be21bac3c73a2332cab681) lapic.c (8d14695f9542e9e0195d6e41ddaa52c32322adf5)
1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.

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135
136#define LVT_MASK \
137 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
138
139#define LINT_MASK \
140 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
141 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
142
1
2/*
3 * Local APIC virtualization
4 *
5 * Copyright (C) 2006 Qumranet, Inc.
6 * Copyright (C) 2007 Novell
7 * Copyright (C) 2007 Intel
8 * Copyright 2009 Red Hat, Inc. and/or its affiliates.

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135
136#define LVT_MASK \
137 (APIC_LVT_MASKED | APIC_SEND_PENDING | APIC_VECTOR_MASK)
138
139#define LINT_MASK \
140 (LVT_MASK | APIC_MODE_MASK | APIC_INPUT_POLARITY | \
141 APIC_LVT_REMOTE_IRR | APIC_LVT_LEVEL_TRIGGER)
142
143static inline int apic_x2apic_mode(struct kvm_lapic *apic)
144{
145 return apic->vcpu->arch.apic_base & X2APIC_ENABLE;
146}
147
148static inline int kvm_apic_id(struct kvm_lapic *apic)
149{
150 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
151}
152
153static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr)
154{
155 u16 cid;

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1298
1299 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1300
1301 return (tpr & 0xf0) >> 4;
1302}
1303
1304void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1305{
143static inline int kvm_apic_id(struct kvm_lapic *apic)
144{
145 return (kvm_apic_get_reg(apic, APIC_ID) >> 24) & 0xff;
146}
147
148static inline u16 apic_cluster_id(struct kvm_apic_map *map, u32 ldr)
149{
150 u16 cid;

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1293
1294 tpr = (u64) kvm_apic_get_reg(vcpu->arch.apic, APIC_TASKPRI);
1295
1296 return (tpr & 0xf0) >> 4;
1297}
1298
1299void kvm_lapic_set_base(struct kvm_vcpu *vcpu, u64 value)
1300{
1301 u64 old_value = vcpu->arch.apic_base;
1306 struct kvm_lapic *apic = vcpu->arch.apic;
1307
1308 if (!apic) {
1309 value |= MSR_IA32_APICBASE_BSP;
1310 vcpu->arch.apic_base = value;
1311 return;
1312 }
1313

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1319 static_key_slow_inc(&apic_hw_disabled.key);
1320 recalculate_apic_map(vcpu->kvm);
1321 }
1322
1323 if (!kvm_vcpu_is_bsp(apic->vcpu))
1324 value &= ~MSR_IA32_APICBASE_BSP;
1325
1326 vcpu->arch.apic_base = value;
1302 struct kvm_lapic *apic = vcpu->arch.apic;
1303
1304 if (!apic) {
1305 value |= MSR_IA32_APICBASE_BSP;
1306 vcpu->arch.apic_base = value;
1307 return;
1308 }
1309

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1315 static_key_slow_inc(&apic_hw_disabled.key);
1316 recalculate_apic_map(vcpu->kvm);
1317 }
1318
1319 if (!kvm_vcpu_is_bsp(apic->vcpu))
1320 value &= ~MSR_IA32_APICBASE_BSP;
1321
1322 vcpu->arch.apic_base = value;
1327 if (apic_x2apic_mode(apic)) {
1328 u32 id = kvm_apic_id(apic);
1329 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1330 kvm_apic_set_ldr(apic, ldr);
1323 if ((old_value ^ value) & X2APIC_ENABLE) {
1324 if (value & X2APIC_ENABLE) {
1325 u32 id = kvm_apic_id(apic);
1326 u32 ldr = ((id >> 4) << 16) | (1 << (id & 0xf));
1327 kvm_apic_set_ldr(apic, ldr);
1328 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, true);
1329 } else
1330 kvm_x86_ops->set_virtual_x2apic_mode(vcpu, false);
1331 }
1331 }
1332
1332 apic->base_address = apic->vcpu->arch.apic_base &
1333 MSR_IA32_APICBASE_BASE;
1334
1335 /* with FSB delivery interrupt, we can restart APIC functionality */
1336 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1337 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1338
1339}

--- 468 unchanged lines hidden --- 		1333 apic->base_address = apic->vcpu->arch.apic_base &
1334 MSR_IA32_APICBASE_BASE;
1335
1336 /* with FSB delivery interrupt, we can restart APIC functionality */
1337 apic_debug("apic base msr is 0x%016" PRIx64 ", and base address is "
1338 "0x%lx.\n", apic->vcpu->arch.apic_base, apic->base_address);
1339
1340}

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