i8259.c (d585a021c0b10b0477d6b608c53e1feb8cde0507) i8259.c (5619c28061ff9d2559a93eaba492935530f2a513)
1#include <linux/linkage.h>
2#include <linux/errno.h>
3#include <linux/signal.h>
4#include <linux/sched.h>
5#include <linux/ioport.h>
6#include <linux/interrupt.h>
7#include <linux/timex.h>
8#include <linux/slab.h>

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27/*
28 * This is the 'legacy' 8259A Programmable Interrupt Controller,
29 * present in the majority of PC/AT boxes.
30 * plus some generic x86 specific things if generic specifics makes
31 * any sense at all.
32 */
33
34static int i8259A_auto_eoi;
1#include <linux/linkage.h>
2#include <linux/errno.h>
3#include <linux/signal.h>
4#include <linux/sched.h>
5#include <linux/ioport.h>
6#include <linux/interrupt.h>
7#include <linux/timex.h>
8#include <linux/slab.h>

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27/*
28 * This is the 'legacy' 8259A Programmable Interrupt Controller,
29 * present in the majority of PC/AT boxes.
30 * plus some generic x86 specific things if generic specifics makes
31 * any sense at all.
32 */
33
34static int i8259A_auto_eoi;
35DEFINE_SPINLOCK(i8259A_lock);
35DEFINE_RAW_SPINLOCK(i8259A_lock);
36static void mask_and_ack_8259A(unsigned int);
37
38struct irq_chip i8259A_chip = {
39 .name = "XT-PIC",
40 .mask = disable_8259A_irq,
41 .disable = disable_8259A_irq,
42 .unmask = enable_8259A_irq,
43 .mask_ack = mask_and_ack_8259A,

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63 */
64unsigned long io_apic_irqs;
65
66void disable_8259A_irq(unsigned int irq)
67{
68 unsigned int mask = 1 << irq;
69 unsigned long flags;
70
36static void mask_and_ack_8259A(unsigned int);
37
38struct irq_chip i8259A_chip = {
39 .name = "XT-PIC",
40 .mask = disable_8259A_irq,
41 .disable = disable_8259A_irq,
42 .unmask = enable_8259A_irq,
43 .mask_ack = mask_and_ack_8259A,

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63 */
64unsigned long io_apic_irqs;
65
66void disable_8259A_irq(unsigned int irq)
67{
68 unsigned int mask = 1 << irq;
69 unsigned long flags;
70
71 spin_lock_irqsave(&i8259A_lock, flags);
71 raw_spin_lock_irqsave(&i8259A_lock, flags);
72 cached_irq_mask |= mask;
73 if (irq & 8)
74 outb(cached_slave_mask, PIC_SLAVE_IMR);
75 else
76 outb(cached_master_mask, PIC_MASTER_IMR);
72 cached_irq_mask |= mask;
73 if (irq & 8)
74 outb(cached_slave_mask, PIC_SLAVE_IMR);
75 else
76 outb(cached_master_mask, PIC_MASTER_IMR);
77 spin_unlock_irqrestore(&i8259A_lock, flags);
77 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
78}
79
80void enable_8259A_irq(unsigned int irq)
81{
82 unsigned int mask = ~(1 << irq);
83 unsigned long flags;
84
78}
79
80void enable_8259A_irq(unsigned int irq)
81{
82 unsigned int mask = ~(1 << irq);
83 unsigned long flags;
84
85 spin_lock_irqsave(&i8259A_lock, flags);
85 raw_spin_lock_irqsave(&i8259A_lock, flags);
86 cached_irq_mask &= mask;
87 if (irq & 8)
88 outb(cached_slave_mask, PIC_SLAVE_IMR);
89 else
90 outb(cached_master_mask, PIC_MASTER_IMR);
86 cached_irq_mask &= mask;
87 if (irq & 8)
88 outb(cached_slave_mask, PIC_SLAVE_IMR);
89 else
90 outb(cached_master_mask, PIC_MASTER_IMR);
91 spin_unlock_irqrestore(&i8259A_lock, flags);
91 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
92}
93
94int i8259A_irq_pending(unsigned int irq)
95{
96 unsigned int mask = 1<<irq;
97 unsigned long flags;
98 int ret;
99
92}
93
94int i8259A_irq_pending(unsigned int irq)
95{
96 unsigned int mask = 1<<irq;
97 unsigned long flags;
98 int ret;
99
100 spin_lock_irqsave(&i8259A_lock, flags);
100 raw_spin_lock_irqsave(&i8259A_lock, flags);
101 if (irq < 8)
102 ret = inb(PIC_MASTER_CMD) & mask;
103 else
104 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
101 if (irq < 8)
102 ret = inb(PIC_MASTER_CMD) & mask;
103 else
104 ret = inb(PIC_SLAVE_CMD) & (mask >> 8);
105 spin_unlock_irqrestore(&i8259A_lock, flags);
105 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
106
107 return ret;
108}
109
110void make_8259A_irq(unsigned int irq)
111{
112 disable_irq_nosync(irq);
113 io_apic_irqs &= ~(1<<irq);

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145 * first, _then_ send the EOI, and the order of EOI
146 * to the two 8259s is important!
147 */
148static void mask_and_ack_8259A(unsigned int irq)
149{
150 unsigned int irqmask = 1 << irq;
151 unsigned long flags;
152
106
107 return ret;
108}
109
110void make_8259A_irq(unsigned int irq)
111{
112 disable_irq_nosync(irq);
113 io_apic_irqs &= ~(1<<irq);

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145 * first, _then_ send the EOI, and the order of EOI
146 * to the two 8259s is important!
147 */
148static void mask_and_ack_8259A(unsigned int irq)
149{
150 unsigned int irqmask = 1 << irq;
151 unsigned long flags;
152
153 spin_lock_irqsave(&i8259A_lock, flags);
153 raw_spin_lock_irqsave(&i8259A_lock, flags);
154 /*
155 * Lightweight spurious IRQ detection. We do not want
156 * to overdo spurious IRQ handling - it's usually a sign
157 * of hardware problems, so we only do the checks we can
158 * do without slowing down good hardware unnecessarily.
159 *
160 * Note that IRQ7 and IRQ15 (the two spurious IRQs
161 * usually resulting from the 8259A-1|2 PICs) occur

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178 outb(0x60+(irq&7), PIC_SLAVE_CMD);
179 /* 'Specific EOI' to master-IRQ2 */
180 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
181 } else {
182 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
183 outb(cached_master_mask, PIC_MASTER_IMR);
184 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
185 }
154 /*
155 * Lightweight spurious IRQ detection. We do not want
156 * to overdo spurious IRQ handling - it's usually a sign
157 * of hardware problems, so we only do the checks we can
158 * do without slowing down good hardware unnecessarily.
159 *
160 * Note that IRQ7 and IRQ15 (the two spurious IRQs
161 * usually resulting from the 8259A-1|2 PICs) occur

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178 outb(0x60+(irq&7), PIC_SLAVE_CMD);
179 /* 'Specific EOI' to master-IRQ2 */
180 outb(0x60+PIC_CASCADE_IR, PIC_MASTER_CMD);
181 } else {
182 inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
183 outb(cached_master_mask, PIC_MASTER_IMR);
184 outb(0x60+irq, PIC_MASTER_CMD); /* 'Specific EOI to master */
185 }
186 spin_unlock_irqrestore(&i8259A_lock, flags);
186 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
187 return;
188
189spurious_8259A_irq:
190 /*
191 * this is the slow path - should happen rarely.
192 */
193 if (i8259A_irq_real(irq))
194 /*

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280}
281
282device_initcall(i8259A_init_sysfs);
283
284void mask_8259A(void)
285{
286 unsigned long flags;
287
187 return;
188
189spurious_8259A_irq:
190 /*
191 * this is the slow path - should happen rarely.
192 */
193 if (i8259A_irq_real(irq))
194 /*

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280}
281
282device_initcall(i8259A_init_sysfs);
283
284void mask_8259A(void)
285{
286 unsigned long flags;
287
288 spin_lock_irqsave(&i8259A_lock, flags);
288 raw_spin_lock_irqsave(&i8259A_lock, flags);
289
290 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
291 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
292
289
290 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
291 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
292
293 spin_unlock_irqrestore(&i8259A_lock, flags);
293 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
294}
295
296void unmask_8259A(void)
297{
298 unsigned long flags;
299
294}
295
296void unmask_8259A(void)
297{
298 unsigned long flags;
299
300 spin_lock_irqsave(&i8259A_lock, flags);
300 raw_spin_lock_irqsave(&i8259A_lock, flags);
301
302 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
303 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
304
301
302 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
303 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
304
305 spin_unlock_irqrestore(&i8259A_lock, flags);
305 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
306}
307
308void init_8259A(int auto_eoi)
309{
310 unsigned long flags;
311
312 i8259A_auto_eoi = auto_eoi;
313
306}
307
308void init_8259A(int auto_eoi)
309{
310 unsigned long flags;
311
312 i8259A_auto_eoi = auto_eoi;
313
314 spin_lock_irqsave(&i8259A_lock, flags);
314 raw_spin_lock_irqsave(&i8259A_lock, flags);
315
316 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
317 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
318
319 /*
320 * outb_pic - this has to work on a wide range of PC hardware.
321 */
322 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */

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351 else
352 i8259A_chip.mask_ack = mask_and_ack_8259A;
353
354 udelay(100); /* wait for 8259A to initialize */
355
356 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
357 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
358
315
316 outb(0xff, PIC_MASTER_IMR); /* mask all of 8259A-1 */
317 outb(0xff, PIC_SLAVE_IMR); /* mask all of 8259A-2 */
318
319 /*
320 * outb_pic - this has to work on a wide range of PC hardware.
321 */
322 outb_pic(0x11, PIC_MASTER_CMD); /* ICW1: select 8259A-1 init */

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351 else
352 i8259A_chip.mask_ack = mask_and_ack_8259A;
353
354 udelay(100); /* wait for 8259A to initialize */
355
356 outb(cached_master_mask, PIC_MASTER_IMR); /* restore master IRQ mask */
357 outb(cached_slave_mask, PIC_SLAVE_IMR); /* restore slave IRQ mask */
358
359 spin_unlock_irqrestore(&i8259A_lock, flags);
359 raw_spin_unlock_irqrestore(&i8259A_lock, flags);
360}
360}