internal.h (798fd4b9ac37fec571f55fb8592497b0dd5f7a73) internal.h (781096d971dfe3c5f9401a300bdb0b148a600584)
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_RESCTRL_INTERNAL_H
3#define _ASM_X86_RESCTRL_INTERNAL_H
4
5#include <linux/resctrl.h>
6#include <linux/sched.h>
7#include <linux/kernfs.h>
8#include <linux/fs_context.h>

--- 22 unchanged lines hidden (view full) ---

31#define QOS_L3_MBM_LOCAL_EVENT_ID 0x03
32
33#define CQM_LIMBOCHECK_INTERVAL 1000
34
35#define MBM_CNTR_WIDTH_BASE 24
36#define MBM_OVERFLOW_INTERVAL 1000
37#define MAX_MBA_BW 100u
38#define MBA_IS_LINEAR 0x4
1/* SPDX-License-Identifier: GPL-2.0 */
2#ifndef _ASM_X86_RESCTRL_INTERNAL_H
3#define _ASM_X86_RESCTRL_INTERNAL_H
4
5#include <linux/resctrl.h>
6#include <linux/sched.h>
7#include <linux/kernfs.h>
8#include <linux/fs_context.h>

--- 22 unchanged lines hidden (view full) ---

31#define QOS_L3_MBM_LOCAL_EVENT_ID 0x03
32
33#define CQM_LIMBOCHECK_INTERVAL 1000
34
35#define MBM_CNTR_WIDTH_BASE 24
36#define MBM_OVERFLOW_INTERVAL 1000
37#define MAX_MBA_BW 100u
38#define MBA_IS_LINEAR 0x4
39#define MBA_MAX_MBPS U32_MAX
40#define MAX_MBA_BW_AMD 0x800
41#define MBM_CNTR_WIDTH_OFFSET_AMD 20
42
43#define RMID_VAL_ERROR BIT_ULL(63)
44#define RMID_VAL_UNAVAIL BIT_ULL(62)
45/*
46 * With the above fields in use 62 bits remain in MSR_IA32_QM_CTR for
47 * data to be returned. The counter width is discovered from the hardware

--- 495 unchanged lines hidden --- 		39#define MAX_MBA_BW_AMD 0x800
40#define MBM_CNTR_WIDTH_OFFSET_AMD 20
41
42#define RMID_VAL_ERROR BIT_ULL(63)
43#define RMID_VAL_UNAVAIL BIT_ULL(62)
44/*
45 * With the above fields in use 62 bits remain in MSR_IA32_QM_CTR for
46 * data to be returned. The counter width is discovered from the hardware

--- 495 unchanged lines hidden ---