generic.c (1809de7e7d37c585e01a1bcc583ea92b78fc759d) | generic.c (c109bf95992b391bb40bc37c5d309d13fead99b5) |
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1/* 2 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong 3 * because MTRRs can span up to 40 bits (36bits on most modern x86) 4 */ 5#define DEBUG 6 7#include <linux/module.h> 8#include <linux/init.h> --- 727 unchanged lines hidden (view full) --- 736 raw_spin_lock(&set_atomicity_lock); 737 738 /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ 739 cr0 = read_cr0() | X86_CR0_CD; 740 write_cr0(cr0); 741 wbinvd(); 742 743 /* Save value of CR4 and clear Page Global Enable (bit 7) */ | 1/* 2 * This only handles 32bit MTRR on 32bit hosts. This is strictly wrong 3 * because MTRRs can span up to 40 bits (36bits on most modern x86) 4 */ 5#define DEBUG 6 7#include <linux/module.h> 8#include <linux/init.h> --- 727 unchanged lines hidden (view full) --- 736 raw_spin_lock(&set_atomicity_lock); 737 738 /* Enter the no-fill (CD=1, NW=0) cache mode and flush caches. */ 739 cr0 = read_cr0() | X86_CR0_CD; 740 write_cr0(cr0); 741 wbinvd(); 742 743 /* Save value of CR4 and clear Page Global Enable (bit 7) */ |
744 if (cpu_has_pge) { | 744 if (boot_cpu_has(X86_FEATURE_PGE)) { |
745 cr4 = __read_cr4(); 746 __write_cr4(cr4 & ~X86_CR4_PGE); 747 } 748 749 /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */ 750 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); 751 __flush_tlb(); 752 --- 13 unchanged lines hidden (view full) --- 766 767 /* Intel (P6) standard MTRRs */ 768 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 769 770 /* Enable caches */ 771 write_cr0(read_cr0() & ~X86_CR0_CD); 772 773 /* Restore value of CR4 */ | 745 cr4 = __read_cr4(); 746 __write_cr4(cr4 & ~X86_CR4_PGE); 747 } 748 749 /* Flush all TLBs via a mov %cr3, %reg; mov %reg, %cr3 */ 750 count_vm_tlb_event(NR_TLB_LOCAL_FLUSH_ALL); 751 __flush_tlb(); 752 --- 13 unchanged lines hidden (view full) --- 766 767 /* Intel (P6) standard MTRRs */ 768 mtrr_wrmsr(MSR_MTRRdefType, deftype_lo, deftype_hi); 769 770 /* Enable caches */ 771 write_cr0(read_cr0() & ~X86_CR0_CD); 772 773 /* Restore value of CR4 */ |
774 if (cpu_has_pge) | 774 if (boot_cpu_has(X86_FEATURE_PGE)) |
775 __write_cr4(cr4); 776 raw_spin_unlock(&set_atomicity_lock); 777} 778 779static void generic_set_all(void) 780{ 781 unsigned long mask, count; 782 unsigned long flags; --- 127 unchanged lines hidden --- | 775 __write_cr4(cr4); 776 raw_spin_unlock(&set_atomicity_lock); 777} 778 779static void generic_set_all(void) 780{ 781 unsigned long mask, count; 782 unsigned long flags; --- 127 unchanged lines hidden --- |