asm-offsets.c (6e2d6b2728fcb408eabd7991804f8cb33ff59f20) asm-offsets.c (5c83511bdb9832c86be20fb86b783356e2f58062)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Generate definitions needed by assembly language modules.
4 * This code generates raw asm output which is post-processed to extract
5 * and format the required data.
6 */
7#define COMPILE_OFFSETS
8

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61 OFFSET(IA32_SIGCONTEXT_ip, sigcontext_32, ip);
62
63 BLANK();
64 OFFSET(IA32_RT_SIGFRAME_sigcontext, rt_sigframe_ia32, uc.uc_mcontext);
65#endif
66
67#ifdef CONFIG_PARAVIRT
68 BLANK();
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * Generate definitions needed by assembly language modules.
4 * This code generates raw asm output which is post-processed to extract
5 * and format the required data.
6 */
7#define COMPILE_OFFSETS
8

--- 52 unchanged lines hidden (view full) ---

61 OFFSET(IA32_SIGCONTEXT_ip, sigcontext_32, ip);
62
63 BLANK();
64 OFFSET(IA32_RT_SIGFRAME_sigcontext, rt_sigframe_ia32, uc.uc_mcontext);
65#endif
66
67#ifdef CONFIG_PARAVIRT
68 BLANK();
69 OFFSET(PARAVIRT_PATCH_pv_cpu_ops, paravirt_patch_template, pv_cpu_ops);
70 OFFSET(PARAVIRT_PATCH_pv_irq_ops, paravirt_patch_template, pv_irq_ops);
71 OFFSET(PV_IRQ_irq_disable, pv_irq_ops, irq_disable);
72 OFFSET(PV_IRQ_irq_enable, pv_irq_ops, irq_enable);
73 OFFSET(PV_CPU_iret, pv_cpu_ops, iret);
74 OFFSET(PV_CPU_read_cr0, pv_cpu_ops, read_cr0);
75 OFFSET(PV_MMU_read_cr2, pv_mmu_ops, read_cr2);
69 OFFSET(PV_IRQ_irq_disable, paravirt_patch_template, irq.irq_disable);
70 OFFSET(PV_IRQ_irq_enable, paravirt_patch_template, irq.irq_enable);
71 OFFSET(PV_CPU_iret, paravirt_patch_template, cpu.iret);
72 OFFSET(PV_CPU_read_cr0, paravirt_patch_template, cpu.read_cr0);
73 OFFSET(PV_MMU_read_cr2, paravirt_patch_template, mmu.read_cr2);
76#endif
77
78#ifdef CONFIG_XEN
79 BLANK();
80 OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask);
81 OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending);
82#endif
83

--- 28 unchanged lines hidden --- 		74#endif
75
76#ifdef CONFIG_XEN
77 BLANK();
78 OFFSET(XEN_vcpu_info_mask, vcpu_info, evtchn_upcall_mask);
79 OFFSET(XEN_vcpu_info_pending, vcpu_info, evtchn_upcall_pending);
80#endif
81

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