apic.h (cf6567fe40c55e9cffca7355cd34e50fb2871e4e) apic.h (ce4e240c279a31096f74afa6584a62d64a1ba8c8)
1#ifndef _ASM_X86_APIC_H
2#define _ASM_X86_APIC_H
3
4#include <linux/cpumask.h>
5#include <linux/delay.h>
6#include <linux/pm.h>
7
8#include <asm/alternative.h>

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103}
104
105extern void native_apic_wait_icr_idle(void);
106extern u32 native_safe_apic_wait_icr_idle(void);
107extern void native_apic_icr_write(u32 low, u32 id);
108extern u64 native_apic_icr_read(void);
109
110#ifdef CONFIG_X86_X2APIC
1#ifndef _ASM_X86_APIC_H
2#define _ASM_X86_APIC_H
3
4#include <linux/cpumask.h>
5#include <linux/delay.h>
6#include <linux/pm.h>
7
8#include <asm/alternative.h>

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103}
104
105extern void native_apic_wait_icr_idle(void);
106extern u32 native_safe_apic_wait_icr_idle(void);
107extern void native_apic_icr_write(u32 low, u32 id);
108extern u64 native_apic_icr_read(void);
109
110#ifdef CONFIG_X86_X2APIC
111/*
112 * Make previous memory operations globally visible before
113 * sending the IPI through x2apic wrmsr. We need a serializing instruction or
114 * mfence for this.
115 */
116static inline void x2apic_wrmsr_fence(void)
117{
118 asm volatile("mfence" : : : "memory");
119}
120
111static inline void native_apic_msr_write(u32 reg, u32 v)
112{
113 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
114 reg == APIC_LVR)
115 return;
116
117 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
118}

--- 452 unchanged lines hidden --- 		121static inline void native_apic_msr_write(u32 reg, u32 v)
122{
123 if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
124 reg == APIC_LVR)
125 return;
126
127 wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
128}

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