sev.c (de4fb176622d54a82ea3ceb7362392aaf5ff0b5a) sev.c (950d00558a920227b5703d1fcc4751cfe03853cd)
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AMD Encrypted Register State Support
4 *
5 * Author: Joerg Roedel <jroedel@suse.de>
6 */
7
8/*

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17#include <asm/trapnr.h>
18#include <asm/trap_pf.h>
19#include <asm/msr-index.h>
20#include <asm/fpu/xcr.h>
21#include <asm/ptrace.h>
22#include <asm/svm.h>
23
24#include "error.h"
1// SPDX-License-Identifier: GPL-2.0
2/*
3 * AMD Encrypted Register State Support
4 *
5 * Author: Joerg Roedel <jroedel@suse.de>
6 */
7
8/*

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17#include <asm/trapnr.h>
18#include <asm/trap_pf.h>
19#include <asm/msr-index.h>
20#include <asm/fpu/xcr.h>
21#include <asm/ptrace.h>
22#include <asm/svm.h>
23
24#include "error.h"
25#include "../msr.h"
25
26struct ghcb boot_ghcb_page __aligned(PAGE_SIZE);
27struct ghcb *boot_ghcb;
28
29/*
30 * Copy a version of this function here - insn-eval.c can't be used in
31 * pre-decompression code.
32 */

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51 */
52static unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx)
53{
54 return 0UL;
55}
56
57static inline u64 sev_es_rd_ghcb_msr(void)
58{
26
27struct ghcb boot_ghcb_page __aligned(PAGE_SIZE);
28struct ghcb *boot_ghcb;
29
30/*
31 * Copy a version of this function here - insn-eval.c can't be used in
32 * pre-decompression code.
33 */

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52 */
53static unsigned long insn_get_seg_base(struct pt_regs *regs, int seg_reg_idx)
54{
55 return 0UL;
56}
57
58static inline u64 sev_es_rd_ghcb_msr(void)
59{
59 unsigned long low, high;
60 struct msr m;
60
61
61 asm volatile("rdmsr" : "=a" (low), "=d" (high) :
62 "c" (MSR_AMD64_SEV_ES_GHCB));
62 boot_rdmsr(MSR_AMD64_SEV_ES_GHCB, &m);
63
63
64 return ((high << 32) | low);
64 return m.q;
65}
66
67static inline void sev_es_wr_ghcb_msr(u64 val)
68{
65}
66
67static inline void sev_es_wr_ghcb_msr(u64 val)
68{
69 u32 low, high;
69 struct msr m;
70
70
71 low = val & 0xffffffffUL;
72 high = val >> 32;
73
74 asm volatile("wrmsr" : : "c" (MSR_AMD64_SEV_ES_GHCB),
75 "a"(low), "d" (high) : "memory");
71 m.q = val;
72 boot_wrmsr(MSR_AMD64_SEV_ES_GHCB, &m);
76}
77
78static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt)
79{
80 char buffer[MAX_INSN_SIZE];
81 int ret;
82
83 memcpy(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE);

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74
75static enum es_result vc_decode_insn(struct es_em_ctxt *ctxt)
76{
77 char buffer[MAX_INSN_SIZE];
78 int ret;
79
80 memcpy(buffer, (unsigned char *)ctxt->regs->ip, MAX_INSN_SIZE);

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