visemul.c (f43dc23d5ea91fca257be02138a255f02d98e806) visemul.c (6cb79b3f3ba2b14590cac02ee13ab7410b6225ed)
1/* visemul.c: Emulation of VIS instructions.
2 *
3 * Copyright (C) 2006 David S. Miller (davem@davemloft.net)
4 */
5#include <linux/kernel.h>
6#include <linux/errno.h>
7#include <linux/thread_info.h>
8#include <linux/perf_event.h>

--- 320 unchanged lines hidden (view full) ---

329 right = edge32_tab[(rs2 >> 2) & 0x1].right;
330 break;
331
332 case EDGE32L_OPF:
333 case EDGE32LN_OPF:
334 left = edge32_tab_l[(rs1 >> 2) & 0x1].left;
335 right = edge32_tab_l[(rs2 >> 2) & 0x1].right;
336 break;
1/* visemul.c: Emulation of VIS instructions.
2 *
3 * Copyright (C) 2006 David S. Miller (davem@davemloft.net)
4 */
5#include <linux/kernel.h>
6#include <linux/errno.h>
7#include <linux/thread_info.h>
8#include <linux/perf_event.h>

--- 320 unchanged lines hidden (view full) ---

329 right = edge32_tab[(rs2 >> 2) & 0x1].right;
330 break;
331
332 case EDGE32L_OPF:
333 case EDGE32LN_OPF:
334 left = edge32_tab_l[(rs1 >> 2) & 0x1].left;
335 right = edge32_tab_l[(rs2 >> 2) & 0x1].right;
336 break;
337 };
337 }
338
339 if ((rs1 & ~0x7UL) == (rs2 & ~0x7UL))
340 rd_val = right & left;
341 else
342 rd_val = left;
343
344 store_reg(regs, rd_val, RD(insn));
345

--- 9 unchanged lines hidden (view full) ---

355 __asm__ __volatile__("subcc %1, %2, %%g0\n\t"
356 "rd %%ccr, %0"
357 : "=r" (ccr)
358 : "r" (orig_rs1), "r" (orig_rs2)
359 : "cc");
360 tstate = regs->tstate & ~(TSTATE_XCC | TSTATE_ICC);
361 regs->tstate = tstate | (ccr << 32UL);
362 }
338
339 if ((rs1 & ~0x7UL) == (rs2 & ~0x7UL))
340 rd_val = right & left;
341 else
342 rd_val = left;
343
344 store_reg(regs, rd_val, RD(insn));
345

--- 9 unchanged lines hidden (view full) ---

355 __asm__ __volatile__("subcc %1, %2, %%g0\n\t"
356 "rd %%ccr, %0"
357 : "=r" (ccr)
358 : "r" (orig_rs1), "r" (orig_rs2)
359 : "cc");
360 tstate = regs->tstate & ~(TSTATE_XCC | TSTATE_ICC);
361 regs->tstate = tstate | (ccr << 32UL);
362 }
363 };
363 }
364}
365
366static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf)
367{
368 unsigned long rs1, rs2, rd_val;
369 unsigned int bits, bits_mask;
370
371 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);

--- 15 unchanged lines hidden (view full) ---

387
388 switch (opf) {
389 case ARRAY16_OPF:
390 rd_val <<= 1;
391 break;
392
393 case ARRAY32_OPF:
394 rd_val <<= 2;
364}
365
366static void array(struct pt_regs *regs, unsigned int insn, unsigned int opf)
367{
368 unsigned long rs1, rs2, rd_val;
369 unsigned int bits, bits_mask;
370
371 maybe_flush_windows(RS1(insn), RS2(insn), RD(insn), 0);

--- 15 unchanged lines hidden (view full) ---

387
388 switch (opf) {
389 case ARRAY16_OPF:
390 rd_val <<= 1;
391 break;
392
393 case ARRAY32_OPF:
394 rd_val <<= 2;
395 };
395 }
396
397 store_reg(regs, rd_val, RD(insn));
398}
399
400static void bmask(struct pt_regs *regs, unsigned int insn)
401{
402 unsigned long rs1, rs2, rd_val, gsr;
403

--- 168 unchanged lines hidden (view full) ---

572 ((rs1 & 0x0000ff00) << 16) |
573 ((rs2 & 0x00ff0000) << 16) |
574 ((rs1 & 0x00ff0000) << 24) |
575 ((rs2 & 0xff000000) << 24) |
576 ((rs1 & 0xff000000) << 32));
577 *fpd_regaddr(f, RD(insn)) = rd_val;
578 break;
579 }
396
397 store_reg(regs, rd_val, RD(insn));
398}
399
400static void bmask(struct pt_regs *regs, unsigned int insn)
401{
402 unsigned long rs1, rs2, rd_val, gsr;
403

--- 168 unchanged lines hidden (view full) ---

572 ((rs1 & 0x0000ff00) << 16) |
573 ((rs2 & 0x00ff0000) << 16) |
574 ((rs1 & 0x00ff0000) << 24) |
575 ((rs2 & 0xff000000) << 24) |
576 ((rs1 & 0xff000000) << 32));
577 *fpd_regaddr(f, RD(insn)) = rd_val;
578 break;
579 }
580 };
580 }
581}
582
583static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
584{
585 struct fpustate *f = FPUSTATE;
586 unsigned long rs1, rs2, rd_val;
587
588 switch (opf) {

--- 99 unchanged lines hidden (view full) ---

688 if (prod & 0x80)
689 scaled++;
690 rd_val |= ((scaled & 0xffffUL) <<
691 ((byte * 32UL) + 7UL));
692 }
693 *fpd_regaddr(f, RD(insn)) = rd_val;
694 break;
695 }
581}
582
583static void pmul(struct pt_regs *regs, unsigned int insn, unsigned int opf)
584{
585 struct fpustate *f = FPUSTATE;
586 unsigned long rs1, rs2, rd_val;
587
588 switch (opf) {

--- 99 unchanged lines hidden (view full) ---

688 if (prod & 0x80)
689 scaled++;
690 rd_val |= ((scaled & 0xffffUL) <<
691 ((byte * 32UL) + 7UL));
692 }
693 *fpd_regaddr(f, RD(insn)) = rd_val;
694 break;
695 }
696 };
696 }
697}
698
699static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf)
700{
701 struct fpustate *f = FPUSTATE;
702 unsigned long rs1, rs2, rd_val, i;
703
704 rs1 = fpd_regval(f, RS1(insn));

--- 76 unchanged lines hidden (view full) ---

781 for (i = 0; i < 2; i++) {
782 s32 a = (rs1 >> (i * 32)) & 0xffff;
783 s32 b = (rs2 >> (i * 32)) & 0xffff;
784
785 if (a == b)
786 rd_val |= 1 << i;
787 }
788 break;
697}
698
699static void pcmp(struct pt_regs *regs, unsigned int insn, unsigned int opf)
700{
701 struct fpustate *f = FPUSTATE;
702 unsigned long rs1, rs2, rd_val, i;
703
704 rs1 = fpd_regval(f, RS1(insn));

--- 76 unchanged lines hidden (view full) ---

781 for (i = 0; i < 2; i++) {
782 s32 a = (rs1 >> (i * 32)) & 0xffff;
783 s32 b = (rs2 >> (i * 32)) & 0xffff;
784
785 if (a == b)
786 rd_val |= 1 << i;
787 }
788 break;
789 };
789 }
790
791 maybe_flush_windows(0, 0, RD(insn), 0);
792 store_reg(regs, rd_val, RD(insn));
793}
794
795/* Emulate the VIS instructions which are not implemented in
796 * hardware on Niagara.
797 */

--- 82 unchanged lines hidden (view full) ---

880 /* Byte Mask and Shuffle Instructions */
881 case BMASK_OPF:
882 bmask(regs, insn);
883 break;
884
885 case BSHUFFLE_OPF:
886 bshuffle(regs, insn);
887 break;
790
791 maybe_flush_windows(0, 0, RD(insn), 0);
792 store_reg(regs, rd_val, RD(insn));
793}
794
795/* Emulate the VIS instructions which are not implemented in
796 * hardware on Niagara.
797 */

--- 82 unchanged lines hidden (view full) ---

880 /* Byte Mask and Shuffle Instructions */
881 case BMASK_OPF:
882 bmask(regs, insn);
883 break;
884
885 case BSHUFFLE_OPF:
886 bshuffle(regs, insn);
887 break;
888 };
888 }
889
890 regs->tpc = regs->tnpc;
891 regs->tnpc += 4;
892 return 0;
893}
889
890 regs->tpc = regs->tnpc;
891 regs->tnpc += 4;
892 return 0;
893}