| tsb.S (ef434a0c2ce765ad33026375db7d23aebd5e9532) | tsb.S (fc290a114fc6034b0f6a5a46e2fb7d54976cf87a) |
|---|---|
| 1/* tsb.S: Sparc64 TSB table handling. 2 * 3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net> 4 */ 5 6 7#include <asm/tsb.h> 8#include <asm/hypervisor.h> --- 346 unchanged lines hidden (view full) --- 355 356 /* Reload MMU related context switch state at 357 * schedule() time. 358 * 359 * %o0: page table physical address 360 * %o1: TSB base config pointer 361 * %o2: TSB huge config pointer, or NULL if none 362 * %o3: Hypervisor TSB descriptor physical address | 1/* tsb.S: Sparc64 TSB table handling. 2 * 3 * Copyright (C) 2006 David S. Miller <davem@davemloft.net> 4 */ 5 6 7#include <asm/tsb.h> 8#include <asm/hypervisor.h> --- 346 unchanged lines hidden (view full) --- 355 356 /* Reload MMU related context switch state at 357 * schedule() time. 358 * 359 * %o0: page table physical address 360 * %o1: TSB base config pointer 361 * %o2: TSB huge config pointer, or NULL if none 362 * %o3: Hypervisor TSB descriptor physical address |
| 363 * %o4: Secondary context to load, if non-zero |
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| 363 * 364 * We have to run this whole thing with interrupts 365 * disabled so that the current cpu doesn't change 366 * due to preemption. 367 */ 368 .align 32 369 .globl __tsb_context_switch 370 .type __tsb_context_switch,#function 371__tsb_context_switch: 372 rdpr %pstate, %g1 373 wrpr %g1, PSTATE_IE, %pstate 374 | 364 * 365 * We have to run this whole thing with interrupts 366 * disabled so that the current cpu doesn't change 367 * due to preemption. 368 */ 369 .align 32 370 .globl __tsb_context_switch 371 .type __tsb_context_switch,#function 372__tsb_context_switch: 373 rdpr %pstate, %g1 374 wrpr %g1, PSTATE_IE, %pstate 375 |
| 376 brz,pn %o4, 1f 377 mov SECONDARY_CONTEXT, %o5 378 379661: stxa %o4, [%o5] ASI_DMMU 380 .section .sun4v_1insn_patch, "ax" 381 .word 661b 382 stxa %o4, [%o5] ASI_MMU 383 .previous 384 flush %g6 385 3861: |
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| 375 TRAP_LOAD_TRAP_BLOCK(%g2, %g3) 376 377 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR] 378 379 ldx [%o1 + TSB_CONFIG_REG_VAL], %o0 380 brz,pt %o2, 1f 381 mov -1, %g3 382 --- 196 unchanged lines hidden --- | 387 TRAP_LOAD_TRAP_BLOCK(%g2, %g3) 388 389 stx %o0, [%g2 + TRAP_PER_CPU_PGD_PADDR] 390 391 ldx [%o1 + TSB_CONFIG_REG_VAL], %o0 392 brz,pt %o2, 1f 393 mov -1, %g3 394 --- 196 unchanged lines hidden --- |