probe.c (98fbe45bea77c1804eae0e71f27673db1824a2a8) probe.c (7863d3f7aeae05099a38693a0a7eb7bdc7b2ab05)
1/*
2 * arch/sh/kernel/cpu/sh4/probe.c
3 *
4 * CPU Subtype Probing for SH-4.
5 *
6 * Copyright (C) 2001 - 2007 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
8 *

--- 120 unchanged lines hidden (view full) ---

129 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
130 CPU_HAS_LLSC;
131 break;
132 case 0x4004:
133 boot_cpu_data.type = CPU_SH7786;
134 boot_cpu_data.icache.ways = 4;
135 boot_cpu_data.dcache.ways = 4;
136 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
1/*
2 * arch/sh/kernel/cpu/sh4/probe.c
3 *
4 * CPU Subtype Probing for SH-4.
5 *
6 * Copyright (C) 2001 - 2007 Paul Mundt
7 * Copyright (C) 2003 Richard Curnow
8 *

--- 120 unchanged lines hidden (view full) ---

129 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
130 CPU_HAS_LLSC;
131 break;
132 case 0x4004:
133 boot_cpu_data.type = CPU_SH7786;
134 boot_cpu_data.icache.ways = 4;
135 boot_cpu_data.dcache.ways = 4;
136 boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
137 CPU_HAS_LLSC | CPU_HAS_PTEAEX;
137 CPU_HAS_LLSC | CPU_HAS_PTEAEX | CPU_HAS_L2_CACHE;
138 break;
139 case 0x3008:
140 boot_cpu_data.icache.ways = 4;
141 boot_cpu_data.dcache.ways = 4;
142 boot_cpu_data.flags |= CPU_HAS_LLSC;
143
144 switch (prr) {
145 case 0x50:

--- 77 unchanged lines hidden (view full) ---

223 /* And the rest of the D-cache */
224 if (boot_cpu_data.dcache.ways > 1) {
225 size = sizes[(cvr >> 16) & 0xf];
226 boot_cpu_data.dcache.way_incr = (size >> 1);
227 boot_cpu_data.dcache.sets = (size >> 6);
228 }
229
230 /*
138 break;
139 case 0x3008:
140 boot_cpu_data.icache.ways = 4;
141 boot_cpu_data.dcache.ways = 4;
142 boot_cpu_data.flags |= CPU_HAS_LLSC;
143
144 switch (prr) {
145 case 0x50:

--- 77 unchanged lines hidden (view full) ---

223 /* And the rest of the D-cache */
224 if (boot_cpu_data.dcache.ways > 1) {
225 size = sizes[(cvr >> 16) & 0xf];
226 boot_cpu_data.dcache.way_incr = (size >> 1);
227 boot_cpu_data.dcache.sets = (size >> 6);
228 }
229
230 /*
231 * Setup the L2 cache desc
232 *
233 * SH-4A's have an optional PIPT L2.
234 */
235 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
231 * SH-4A's have an optional PIPT L2.
232 */
233 if (boot_cpu_data.flags & CPU_HAS_L2_CACHE) {
236 /* Bug if we can't decode the L2 info */
237 BUG_ON(!(cvr & 0xf));
238
239 /* Silicon and specifications have clearly never met.. */
240 cvr ^= 0xf;
241
242 /*
234 /*
243 * Size calculation is much more sensible
244 * than it is for the L1.
245 *
246 * Sizes are 128KB, 258KB, 512KB, and 1MB.
235 * Verify that it really has something hooked up, this
236 * is the safety net for CPUs that have optional L2
237 * support yet do not implement it.
247 */
238 */
248 size = (cvr & 0xf) << 17;
239 if ((cvr & 0xf) == 0)
240 boot_cpu_data.flags &= ~CPU_HAS_L2_CACHE;
241 else {
242 /*
243 * Silicon and specifications have clearly never
244 * met..
245 */
246 cvr ^= 0xf;
249
247
250 BUG_ON(!size);
248 /*
249 * Size calculation is much more sensible
250 * than it is for the L1.
251 *
252 * Sizes are 128KB, 258KB, 512KB, and 1MB.
253 */
254 size = (cvr & 0xf) << 17;
251
255
252 boot_cpu_data.scache.way_incr = (1 << 16);
253 boot_cpu_data.scache.entry_shift = 5;
254 boot_cpu_data.scache.ways = 4;
255 boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
256 boot_cpu_data.scache.way_incr = (1 << 16);
257 boot_cpu_data.scache.entry_shift = 5;
258 boot_cpu_data.scache.ways = 4;
259 boot_cpu_data.scache.linesz = L1_CACHE_BYTES;
256
260
257 boot_cpu_data.scache.entry_mask =
258 (boot_cpu_data.scache.way_incr -
259 boot_cpu_data.scache.linesz);
261 boot_cpu_data.scache.entry_mask =
262 (boot_cpu_data.scache.way_incr -
263 boot_cpu_data.scache.linesz);
260
264
261 boot_cpu_data.scache.sets = size /
262 (boot_cpu_data.scache.linesz *
263 boot_cpu_data.scache.ways);
265 boot_cpu_data.scache.sets = size /
266 (boot_cpu_data.scache.linesz *
267 boot_cpu_data.scache.ways);
264
268
265 boot_cpu_data.scache.way_size =
266 (boot_cpu_data.scache.sets *
267 boot_cpu_data.scache.linesz);
269 boot_cpu_data.scache.way_size =
270 (boot_cpu_data.scache.sets *
271 boot_cpu_data.scache.linesz);
272 }
268 }
269
270 return 0;
271}
273 }
274
275 return 0;
276}