probe.c (1da177e4c3f41524e886b7f1b8a0c1fc7321cac2) probe.c (9d4436a6fbc8c5eccdfcb8f5884e0a7b4a57f6d2)
1/*
2 * arch/sh/kernel/cpu/sh2/probe.c
3 *
4 * CPU Subtype Probing for SH-2.
5 *
6 * Copyright (C) 2002 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13
14#include <linux/init.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17
18int __init detect_cpu_and_cache_system(void)
19{
1/*
2 * arch/sh/kernel/cpu/sh2/probe.c
3 *
4 * CPU Subtype Probing for SH-2.
5 *
6 * Copyright (C) 2002 Paul Mundt
7 *
8 * This file is subject to the terms and conditions of the GNU General Public
9 * License. See the file "COPYING" in the main directory of this archive
10 * for more details.
11 */
12
13
14#include <linux/init.h>
15#include <asm/processor.h>
16#include <asm/cache.h>
17
18int __init detect_cpu_and_cache_system(void)
19{
20 /*
21 * For now, assume SH7604 .. fix this later.
22 */
20#if defined(CONFIG_CPU_SUBTYPE_SH7604)
23 cpu_data->type = CPU_SH7604;
24 cpu_data->dcache.ways = 4;
21 cpu_data->type = CPU_SH7604;
22 cpu_data->dcache.ways = 4;
25 cpu_data->dcache.way_shift = 6;
23 cpu_data->dcache.way_incr = (1<<10);
26 cpu_data->dcache.sets = 64;
27 cpu_data->dcache.entry_shift = 4;
28 cpu_data->dcache.linesz = L1_CACHE_BYTES;
29 cpu_data->dcache.flags = 0;
24 cpu_data->dcache.sets = 64;
25 cpu_data->dcache.entry_shift = 4;
26 cpu_data->dcache.linesz = L1_CACHE_BYTES;
27 cpu_data->dcache.flags = 0;
30
28#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
29 cpu_data->type = CPU_SH7619;
30 cpu_data->dcache.ways = 4;
31 cpu_data->dcache.way_incr = (1<<12);
32 cpu_data->dcache.sets = 256;
33 cpu_data->dcache.entry_shift = 4;
34 cpu_data->dcache.linesz = L1_CACHE_BYTES;
35 cpu_data->dcache.flags = 0;
36#endif
31 /*
32 * SH-2 doesn't have separate caches
33 */
34 cpu_data->dcache.flags |= SH_CACHE_COMBINED;
35 cpu_data->icache = cpu_data->dcache;
36
37 return 0;
38}
39
37 /*
38 * SH-2 doesn't have separate caches
39 */
40 cpu_data->dcache.flags |= SH_CACHE_COMBINED;
41 cpu_data->icache = cpu_data->dcache;
42
43 return 0;
44}
45